ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 42

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF542/4/7/8/9
Table 25. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
S = number of programmed setup cycles, WA = number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
DANR
HAA
DDAT
ENDAT
DO
HO
ADDR19–1
DATA15–0
CLKOUT
ABE1–0
AMSx
ARDY
AWE
ARDY Negated Delay from AMSx Asserted
ARDY Asserted Hold After ARE Negated
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
t
ENDAT
SETUP
t
t
DANW
DO
Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
t
DO
BE, ADDRESS
WRITE DATA
PROGRAMMED WRITE
ACCESS 2 CYCLES
2
2
Rev. PrG | Page 42 of 82 | December 2007
1
EXTENDED
ACCESS
t
HO
1 CYCLE
HOLD
Preliminary Technical Data
t
HAA
t
HO
Min
0.0
1.0
0.8
Max
(S+WA–2)*t
6.0
6.0
SCLK
Unit
ns
ns
ns
ns
ns
ns