ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 63

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
JTAG Test And Emulation Port Timing
Table 49
Table 49. JTAG Port Timing
1
2
3
Parameter
Timing Parameters
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, CLKIN, RESET, NMI,
50 MHz Maximum
System Outputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
BMODE3–0, MFS, MLF_P, and MLF_M.
DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, EMU, CLKOUT, CLKBUF, EXT_WAKE.
and
Figure 33
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulsewidth
TDO Delay from TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
OUTPUTS
SYSTEM
TCK
TMS
TDO
INPUTS
SYSTEM
TDI
2
(measured in TCK cycles)
t
DSYS
t
Rev. PrG | Page 63 of 82 | December 2007
DTDO
t
SSYS
t
STAP
1
3
1
Figure 33. JTAG Port Timing
t
TCK
t
HSYS
t
HTAP
ADSP-BF542/4/7/8/9
Minimum
20
4
4
4
5
4
0
Maximum
10
12
Unit
ns
ns
ns
ns
ns
TCK
ns
ns