ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
The fourth memory block is the factory programmed L1
instruction ROM, operating at full processor speed. This ROM
is not customer configurable.
The fifth memory block is the L2 SRAM, providing 128K bytes
of unified instruction and data memory, operating at one half
the frequency of the core.
Finally, there is a 4K boot ROM connected as L3 memory. It
operates at full SCLK rate.
External (Off-Chip) Memory
Through the External Bus Interface Unit (EBIU) the
ADSP-BF542/4/7/8/9 processors provide glueless connectivity
to external 16-bit wide memories, such as DDR SDRAM,
Mobile DDR, SRAM, NOR flash, NAND flash, and FIFO
devices. To provide the best performance, the bus system of the
DDR interface is completely separate from the other parallel
interfaces.
The DDR/Mobile DDR memory controller can gluelessly man-
age up to two banks of double-rate synchronous dynamic
memory (DDR1 SDRAM). The 16-bit wide interface operates at
SCLK frequency, enabling maximum throughput of 532
Mbyte/s. The DDR controller is augmented with a queuing
mechanism that performs efficient bursts into the DDR. The
controller is an industry standard DDR1 SDRAM controller
with each bank supporting from 64 Mbit to 512 Mbit device
sizes and 4-, 8-, or 16-bit widths. The controller supports up to
256 Mbytes per external bank. With 2 external banks, the con-
troller supports up to 512 Mbytes total. Each bank is
independently programmable and is contiguous with adjacent
banks regardless of the sizes of the different banks or their
placement.
Traditional 16-bit asynchronous memories, such as SRAM,
EPROM, and flash devices, can be connected to one of the four
64 MByte asynchronous memory banks, represented by four
memory select strobes. Alternatively, these strobes can function
as bank-specific read or write strobes preventing further glue
logic when connecting to asynchronous FIFO devices.
In addition, the external bus can connect to advanced flash
device technologies, such as:
NAND Flash Controller (NFC)
The ADSP-BF542/4/7/8/9 provides a NAND Flash Controller
(NFC) as part of the external bus interface. NAND flash devices
provide high-density, low-cost memory. However, NAND flash
devices also have long random access times, invalid blocks, and
lower reliability over device lifetimes. Because of this, NAND
flash is often used for read-only code storage. In this case, all
DSP code can be stored in NAND flash and then transferred to a
faster memory (such as DDR or SRAM) before execution.
• Page-mode NOR flash devices
• Synchronous burst-mode NOR flash devices
• NAND flash devices
Rev. PrG | Page 7 of 82 | December 2007
Another common use of NAND flash is for storage of multime-
dia files or other large data segments. In this case, a software file
system may be used to manage reading and writing of the
NAND flash device. The file system selects memory segments
for storage with the goal of avoiding bad blocks and equally dis-
tributing memory accesses across all address locations.
Hardware features of the NFC include:
One-time-Programmable Memory
The ADSP-BF542/4/7/8/9 has 64K bits of one-time program-
mable (OTP) non-volatile memory that can be programmed by
the developer only one time. It includes the array and logic to
support read access and programming. Additionally, its pages
can be write protected.
OTP enables developers to store both public and private data
on-chip. In addition to storing public and private key data for
applications requiring security, it also allows developers to store
completely user-definable data such as customer ID, product
ID, MAC address, etc. Hence generic parts can be shipped
which are then programmed and protected by the developer
within this non-volatile memory.
I/O Memory Space
The ADSP-BF542/4/7/8/9 processors do not define a separate
I/O space. All resources are mapped through the flat 32-bit
address space. On-chip I/O devices have their control registers
mapped into memory-mapped registers (MMRs) at addresses
near the top of the 4G byte address space. These are separated
into two smaller blocks, one which contains the control MMRs
for all core functions, and the other which contains the registers
needed for setup and control of the on-chip peripherals outside
of the core. The MMRs are accessible only in supervisor mode
and appear as reserved space to on-chip peripherals.
Booting
The ADSP-BF542/4/7/8/9 processor contains a small on-chip
boot kernel, which configures the appropriate peripheral for
booting. If the ADSP-BF542/4/7/8/9 processor is configured to
• Support for page program, page read, and block erase of
• Error checking and correction (ECC) hardware that facili-
• A single 8-bit or 16-bit external bus interface for com-
• Support for SLC (single level cell) NAND flash devices
• Capability of releasing external bus interface pins during
• Support for internal bus requests of 16 or 32 bits.
• DMA engine to transfer data between internal memory and
NAND flash devices, with accesses aligned to page
boundaries.
tates error detection and correction.
mands, addresses and data.
unlimited in size, with page sizes of 256 and 512 bytes.
Larger page sizes can be supported in software.
long accesses.
NAND flash device.
ADSP-BF542/4/7/8/9