ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 31

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 12. Pin Descriptions (Continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Name
Clock (PLL) Pins
CLKIN
CLKOUT
XTAL
CLKBUF
EXT_WAKE
RESET
NMI
Supplies
V
V
V
V
V
V
GND
V
GND
I = Input, O = Output, P =Power, G = Ground, C = Crystal, A = Analog.
To use the SPI memory boot, SCLK0 should have a pulldown, MISO should have a pullup, and SPISEL1 is used as CS with a pullup.
To use the serial TWI memory boot, SDA0 and SCL0 should have a pullup.
By default the ATAPI bus shares the data pins D0-15 and the address pins A0-2 with the asynchronous memory interface and the NAND controller. When PORTF_MUX[1:0]
The Boot Host Wait (HWAIT) signal on PB11 is a GPIO output that is driven and toggled by the boot kernel at boot time. An external pulling resistor is required for proper
This pin should not be used as GPIO if booting in mode 1.
This pin should always be enabled as ND_CE in software and pulled HIGH with a resistor when using NAND flash.
This pin should always be enabled as bus request in software and pulled HIGH to enable the Async access.
For the ADSP-BF542/4/7/8/9, the unused USB pins should be terminated as follows: USB_DP --> GND; USB_DM -->GND; USB_XTALIN --> GND; USB_XTALOUT -->
In the case that USB is used in device mode only, the USB_ID pin should be either pulled HIGH or left unconnected.
This pin should be pulled LOW if the JTAG port will not be used.
Always connect VR
This pin should always be pulled HIGH when not used.
Power and ground pins of peripherals should be driven to their specified level even if the associated peripheral is not used in the application.
The VDDVR pin must always be connected. If the internal voltage regulator is not being used, this pin may be connected to VDDEXT. Otherwise it should be powered
Analog ground for MXVR.
Connect to GND when MXVR is not used.
This pin should always be pulled either HIGH or LOW, but must not be left floating.
= b#01, then the ATAPI data bus is available through Port F and the address line can be found at Port G.
operation. A pull-up resistor instructs the HWAIT signal to behave active high (low when ready for data). A pull-down resistor instructs the HWAIT signal to behave active
low (high when ready for data). After boot it can be used for other purposes. If the PB11 pin is required for other purposes (for example, timer or SPI operation) the Alternate
Boot Host Wait (HWAITA) on PH7 can be used instead. This is enabled by programming the OTP_ALTERNATE_HWAIT bit in the PBS00L OTP memory page.
NC (No Connect); USB_ID --> VSS; USB_VREF --> NC; USB_RSET --> NC; USB_VBUS --> VSS; VDDUSB --> VDDEXT
according to the VDDVR specification.
DDINT
DDEXT
DDDDR
DDUSB
DDRTC
DDVR
DDMP
14
MP
16
15
15
15
17, 18
OUT
0 and VR
OUT
1 together to reduce signal impedance.
Rev. PrG | Page 31 of 82 | December 2007
I/O
C
O
C
O
I
I
P
P
P
P
P
P
G
P
G
O
1
Function (First/Second/Third/Fourth)
Clock/Crystal Input
Clock Output
Crystal Output
External Wakeup from hibernate output
Reset
Non-maskable Interrupt
Internal Power Supply
External Power Supply
External DDR Power Supply
External USB Power Supply
RTC Clock Supply
Internal Voltage Regulator Power Supply
Ground
MXVR PLL Power Supply
MXVR PLL Ground
Buffered Oscillator output
ADSP-BF542/4/7/8/9