ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 62

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF542/4/7/8/9
HOSTDP A/C Timing- Host Write Cycle
Table 47
requirements.
Table 47. Host Write Cycle Timing Requirements
Table 48. OTP Timing Parameters
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
Parameter
t
t
t
t
t
These parameters are programmed into the OTP_TIMING register. See ADSP-BF54x Blackfin Processor Hardware Reference for details.
SADWRH
HADWRH
WRWL
WRWH
DWRHRDY
HDATWH
SDATWH
DRDYWRL
RDYPWR
FACC
RPGM
CPS
CPH
PGM
describes the HOSTDP A/C Host Write Cycle timing
HOST_ADDR/Host_CE Setup before Host_WR
HOST_ADDR/Host_CE Hold after Host_WR
Host_WR pulse width low
Host_WR pulse width high
Host_WR de-assertion delay after Host_ACK
de-assertion
Data Hold after Host_WR de-assertion
Data Setup before Host_WR de-assertion
Host_ACK low delay after Host_WR/Host_CE
Host_ACK low pulse-width for Write access
OTP Memory Bit Read Access Time
OTP Memory Charge Pump Release Time
OTP Memory Charge Pump Setup Time
OTP Memory Charge Pump Hold Time
OTP Memory Bit Program Time
HOST_ADDR
HOST_D15-0
HOST_ACK
HOST_CE
HOST_WR
1
t
DRDYWRL
Rev. PrG | Page 62 of 82 | December 2007
t
SDATWH
Figure 32. HOSTDP A/C- Host Write Cycle
t
RDYPWR
t
SADWRH
t
WRWL
2.5
Minimum
(1.5 * t
2.5
t
mode)
1.5 * t
2 * t
TBD
2.5
DRDYWRL
sclk
sclk
+ t
sclk
+ 8.7 (INT mode)
)+ 10.8
RDYPRD
t
t
+ t
DWRHRDY
HDATWH
DWRHRDY
t
HADWRH
t
WRWH
(ACK
wrh
Maximum
1.5 * t
Preliminary Technical Data
sclk
Minimum
400
1
10
Maximum
0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
s
s
s
s