T89C51RD2-3CBC-L ATMEL [ATMEL Corporation], T89C51RD2-3CBC-L Datasheet - Page 11

• Manufacturer Part Number: T89C51RD2-3CBC-L
• Description: 0 to 40MHz Flash Programmable 8-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

T89C51RD2
The X2 bit in the CKCON register (See Table 2.) allows to switch from 12 clock periods per instruction to 6
clock periods and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the
X2 feature (X2 mode).
The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (See Table 2.) allow to switch from
standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods
per peripheral clock cycle). These bits are active only in X2 mode.
More information about the X2 mode can be found in the application note ANM072 "How to take advantage of
the X2 features in TS80C51 microcontroller?"
CKCON - Clock Control Register (8Fh)
11
Number
XTAL1
XTAL1:2
X2 bit
CPU clock
Bit
7
6
5
4
3
2
7
-
Mnemonic
WdX2
PcaX2
T2X2
T1X2
SiX2
STD Mode
Bit
WdX2
-
6
Reserved
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect)
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Set to select 12 clock periods per peripheral clock cycle.
Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Clear to select 6 clock periods per peripheral clock cycle.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
PcaX2
5
Figure 2. Mode Switching Waveforms
Table 2. CKCON Register
SiX2
4
X2 Mode
T2X2
3
Description
T1X2
2
Rev. F - 15 February, 2001
T0X2
1
STD Mode
X2
0