T89C51RD2-3CBC-L ATMEL [ATMEL Corporation], T89C51RD2-3CBC-L Datasheet - Page 44

• Manufacturer Part Number: T89C51RD2-3CBC-L
• Description: 0 to 40MHz Flash Programmable 8-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

T89C51RD2
WDTPRG Address (0A7h)
Reset value XXXX X000
6.10.2. WDT during Power Down and Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the T89C51RD2
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T89C51RD2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.
If the WDT is activated, the power consumption in stand-by mode will be above the specified value.
44
Number
Bit
7
6
5
4
3
2
1
0
T4
7
Mnemonic
Bit
T4
T3
T2
T1
T0
S2
S1
S0
T3
6
Reserved
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
The value read from this bit is undeterminated. Do not try to set this bit..
S2
0
0
0
0
1
1
1
1
T2
S1S0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
5
Table 22. WDTPRG Register
(2
Selected Time-out
(2
(2
(2
(2
(2
(2
(2
17
14
15
16
18
19
20
21
- 1) machine cycles, 131 ms @ 12 MHz
- 1) machine cycles, 16.3 ms @ 12 MHz
- 1) machine cycles, 32.7 ms @ 12 MHz
- 1) machine cycles, 65.5 ms @ 12 MHz
- 1) machine cycles, 262 ms @ 12 MHz
- 1) machine cycles, 542 ms @ 12 MHz
- 1) machine cycles, 1.05 s @ 12 MHz
- 1) machine cycles, 2.09 s @ 12 MHz
T1
4
T0
3
Description
S2
2
Rev. F - 15 February, 2001
S1
1
S0
0