T89C51RD2-3CBC-L ATMEL [ATMEL Corporation], T89C51RD2-3CBC-L Datasheet - Page 33

• Manufacturer Part Number: T89C51RD2-3CBC-L
• Description: 0 to 40MHz Flash Programmable 8-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

T89C51RD2
6.6.2. Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled
(SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
6.6.3. Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte
that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the
flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
The following is an example of how to use given addresses to address different slaves:
Slave A:
Slave B:
Slave C:
33
SADDR
SADEN
Given
SADDR
SADEN
Given
SADDR
SADEN
Given
SADDR
SADEN
Given
SMOD0=0
SMOD0=1
SMOD0=1
0101 0110b
1111 1100b
0101 01XXb
1111 0001b
1111 1010b
1111 0X0Xb
1111 0011b
1111 1001b
1111 0XX1b
1111 0010b
1111 1101b
1111 00X1b
RXD
FE
RI
RI
Figure 15. UART Timings in Modes 2 and 3
Start
bit
D0
D1
D2
D3
Data byte
D4
D5
D6
D7
Rev. F - 15 February, 2001
Ninth
D8
bit
Stop
bit