T89C51RD2-3CBC-L ATMEL [ATMEL Corporation], T89C51RD2-3CBC-L Datasheet - Page 20

• Manufacturer Part Number: T89C51RD2-3CBC-L
• Description: 0 to 40MHz Flash Programmable 8-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

T89C51RD2
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
20
Number
Bit
TF2
7
6
5
4
3
2
1
0
7
Mnemonic
CP/RL2#
EXEN2
RCLK
TCLK
C/T2#
EXF2
TF2
TR2
Bit
EXF2
6
Timer 2 overflow Flag
Timer 2 External Flag
Receive Clock bit
Transmit Clock bit
Timer 2 External Enable bit
clock the serial port.
Timer 2 Run control bit
Timer/Counter 2 select bit
Timer 2 Capture/Reload bit
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
Clear to turn off timer 2.
Set to turn on timer 2.
Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
RCLK
5
Table 5. T2CON Register
TCLK
4
EXEN2
3
Description
TR2
OSC
2
).
Rev. F - 15 February, 2001
C/T2#
1
CP/RL2#
0