MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet
MT46V64M16P-6T IT:A
Related parts for MT46V64M16P-6T IT:A
MT46V64M16P-6T IT:A Summary of contents
Page 1
... See Table 3 on page 2 for module compatibility. Data-Out Access Window Window 1.6ns ±0.70ns 2.0ns ±0.70ns 2.5ns ±0.75ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Features Marking 256M4 128M8 64M16 -5B -6T ...
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... Meg Meg banks 32 Meg banks 8K 16K (A0–A13) 4 (BA0, BA1) 4K (A0–A9, A11, A12) Yes Yes Yes Yes – – -6T -75 Example Part Number: MT46V64M16P-6T:A - Sp. Configuration Package Speed Op. Temp. 256M4 128M8 64M16 IT Special Options TG P Speed Grade ...
Page 3
... SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Power-down (CKE Not Active .81 PDF: 09005aef80a2f898/Source: 09005aef82a95a3a 1Gb_DDRTOC.fm - 1Gb DDR: Rev. J, Core DDR: Rev. E 7/11 EN 1Gb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2003 Micron Technology, Inc. All rights reserved. Table of Contents ...
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... ACT = ACTIVE BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 1Gb: x4, x8, x16 DDR SDRAM State Diagram Self refresh REFS ...
Page 5
... Any specific requirement takes precedence over a general statement. PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN 1Gb: x4, x8, x16 DDR SDRAM Functional Description Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 ©2000 Micron Technology, Inc. All rights reserved. ...
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... I/O gating 2 DM mask logic 8 Bank control logic 2048 Column decoder Column- 11 address counter/ latch 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 6 1Gb: x4, x8, x16 DDR SDRAM Functional Block Diagrams CK DLL Data READ MUX latch DRVRS 4 1 DQS ...
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... WRITE 4 32 FIFO RCVRS and 16 16 drivers Data in out CK 1 Column 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. DQ0–DQ7 DQS DM DQ0–DQ15 DQS L/H LDM, UDM ...
Page 8
... BA1 27 A10/AP A10/ Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 1Gb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions x16 DQ7 NF 65 DQ15 ...
Page 9
... Pin and x8. Supply Power supply. Supply DQ power supply: Isolated on the die for improved noise immunity. Micron Technology, Inc., reserves the right to change products or specifications without notice. 9 1Gb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions is applied and until CKE is first brought DD © ...
Page 10
... No connect for x4: These pins should be left unconnected. – No function for x4: These pins should be left unconnected. – Do not use: Must float to minimize noise on V Micron Technology, Inc., reserves the right to change products or specifications without notice. 10 1Gb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions . ...
Page 11
... DDR: Rev. J, Core DDR: Rev. E 7/11 EN See detail A 0.71 0.10 (2X) 11.76 ±0.20 10.16 ±0.08 +0.03 0.15 –0.02 0.10 0.10 1.20 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 1Gb: x4, x8, x16 DDR SDRAM Package Dimensions Gage plane +0.10 –0.05 Detail A ©2003 Micron Technology, Inc. All rights reserved. 0.25 0.80 TYP 0.50 ±0.10 ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. DD Units Notes ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. DD Units Notes ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 14 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – RFC REFI CL 9 n/a n/a n/a 10 n/a n/a n/a 11 n/a n/a n/a 9 n/a n/a 2.5 10 n/a n/a 2.5 11 n/a n/a 3 n/a n/a n/a 2.5 n/a n/a n/a 2.5 n/a n/a n/a 3 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n n/a n n/a n n/a n/a 16 1,026 n/a n/a 20 ...
Page 15
... I OHR OUT - 0.373V, minimum ) OUT OLR , REF ) Micron Technology, Inc., reserves the right to change products or specifications without notice. 15 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Min Max –1V 3.6V –1V 3.6V –1V 3.6V –0. 0.5V DDQ –55 150 – 2.6V ± ...
Page 16
... OLR , REF ) 2.5V ±0.2V 2.5V ±0. DDQ Symbol V IH(AC) V IL(AC) V REF(AC) Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC = 2.5V ±0.2V, V DDQ DD Min Max Units 2.3 2.7 V 2.3 2.7 V 0.49 × V 0.51 × DDQ ...
Page 17
... V (MAX) (0.83V for SSTL_2 OL termination) VssQ with test load is 1.927V. with test load is 0.373V 25Ω Reference 25Ω point Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 1Gb: x4, x8, x16 DDR SDRAM noise ...
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... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev 2.5V ±0.2V 2.5V ±0. DDQ Symbol V MP(DC) V IN(DC) V ID(DC) V ID(AC) V 0.5 × V IX(AC) X ID(DC) ,min Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC = 2.6V ±0.1V 2.6V ±0.1V for -5B) DD Min Max Units 1.15 1.35 –0 0.3 DDQ 0. 0.6 DDQ ...
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... 2.0 I3 Symbol Min DC – IOL DC – IOU DC – – 2.0 I3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 19 Max Units Notes 5.0 pF 3.0 pF 3.0 pF 3.0 pF Max Units Notes 0.25 ...
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... RFC t REFI t RFC RPRE t RPST t RRD t VTD t WPRE t WPRES t WPST t WR Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units –0.70 0. 0. 7.5 13 ...
Page 21
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev 2.6V ±0.1V 2.6V ±0.1V DD Symbol t WTR t 1Gb XSNR t XSRD n/a Micron Technology, Inc., reserves the right to change products or specifications without notice. 21 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units t 2 – CK 126 – ...
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... REFI t RFC 1Gb RPRE t RPST t RRD t VTD t WPRE t WPRES t WPST Micron Technology, Inc., reserves the right to change products or specifications without notice. 22 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6T (TSOP) Min Max Units –0.70 0. 0. ...
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... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev 2.5V ±0.2V 2.5V ±0.2V DD Symbol WTR t XSNR 1Gb t XSRD n/a Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6T (TSOP) Min Max Units 15 – – CK 126 – ...
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... REFI t 1Gb RFC RPRE t RPST t RRD t VTD t WPRE t WPRES tWPST tWR Micron Technology, Inc., reserves the right to change products or specifications without notice. 24 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75 Min Max Units –0.75 0. 0.45 0. ...
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... XSNR t XSRD n/a = 2.5V ±0.2V 2.5V ±0. 1.00 1.05 1.10 = 2.5V ±0.2V 2.5V ±0. 0.50 0.55 0.60 Micron Technology, Inc., reserves the right to change products or specifications without notice. 25 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75 Min Max Units t 1 – CK 127.5 – 200 – ...
Page 26
... REF /2, V (peak-to-peak) = 0.2V. DM input is DDQ OUT t IS has an additional 50ps per each t IH has 0ps added, that is, it Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. may not REF = ...
Page 27
... CK that meets t RAS (MAX) for I CK that meets the maximum absolute value for RFC [MIN]), else CKE is LOW (that is, during Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. mea CK/2), ...
Page 28
... CK = 7.5ns -75E / - 7.5ns - 6ns - 6ns - 5ns 2.56 2.53 2.49 2.45 2.41 2.31 2.28 2.24 2.20 2.16 1.95 1.92 1.89 1.86 1.83 1.85 1.82 1.79 1.76 1.73 1.48 1.45 1.43 1.40 1.38 47/53 46/ (MIN) actually applied to the device CK 300mV or 2.2V (2.4V for -5B), – Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. 2.38 2.13 1.80 1.70 1.35 45/55 t RAS (MIN) ...
Page 29
... V-I curve of Figure 14. 29 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 2.0 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. ...
Page 30
... DD pulse width d 3ns, and the pulse width undershoot IL,min t RPST (MAX) condition. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. 1.5V for a pulse – (MIN) will ...
Page 31
... V the input pin. 46. The current Micron part operates below 83 MHz (slowest specified JEDEC operating frequency). As such, future die may not reflect this option. 47. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. 48. Random address is changing ...
Page 32
... Micron Technology, Inc., reserves the right to change products or specifications without notice. 32 1Gb: x4, x8, x16 DDR SDRAM Pull-Up Current (mA) Nominal High Min Max –7.6 –4.6 –10.0 –14.5 –9.2 –20.0 –21.2 –13.8 – ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 1Gb: x4, x8, x16 DDR SDRAM Pull-Up Current (mA) Nominal High Min Max –4.3 –2.6 –5.0 –7.8 –5.2 –9.9 –12.0 –7.8 –14.6 –15.7 –10.4 –19.2 – ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 34 Commands Address Notes Bank/row 2 Bank/col 3 L Bank/col Code Op-code 8 DQ ...
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... RCD has been met. No data has been met. Once RP is met, the bank has been met. Once RP is met, the bank Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Commands Notes ...
Page 36
... XSNR has been met (if the previous state was self refresh). 36 1Gb: x4, x8, x16 DDR SDRAM is HIGH (see Table 27 on page 38) and n Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Commands t RFC ...
Page 37
... Minimum Delay with Concurrent Auto Precharge (BL/2)] × WTR t (BL/2) × (BL/2) × [CL + (BL/2)] × Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Commands t WR measured as ...
Page 38
... RPST); for a WRITE, CKE must stay HIGH until the must be powered within the spec- REF t MRD is met. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Commands Notes 7 t XSNR period. ...
Page 39
... PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN HIGH Row Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 39 1Gb: x4, x8, x16 DDR SDRAM Commands ©2000 Micron Technology, Inc. All rights reserved. ...
Page 40
... PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN HIGH Col EN AP DIS AP Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 40 1Gb: x4, x8, x16 DDR SDRAM Commands ©2000 Micron Technology, Inc. All rights reserved. ...
Page 41
... Ai is the most significant column address bit for a given density ( HIGH Col EN AP DIS AP Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 1Gb: x4, x8, x16 DDR SDRAM Commands ©2000 Micron Technology, Inc. All rights reserved. ...
Page 42
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN HIGH All banks One bank Bank1 Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 42 1Gb: x4, x8, x16 DDR SDRAM Commands ©2000 Micron Technology, Inc. All rights reserved. ...
Page 43
... Issue an AUTO REFRESH command. This may be moved prior to step 13. 18. Wait at least 19. Although not required by the Micron device, JEDEC requires an LMR command to clear the DLL bit (set LMR command is issued, the same operating parameters should be utilized as in step 11. ...
Page 44
... Assert NOP or DESELECT for t RFC time Optional LMR command to clear DLL bit Assert NOP or DESELECT for t MRD time DRAM is ready for any valid command Micron Technology, Inc., reserves the right to change products or specifications without notice. 44 1Gb: x4, x8, x16 DDR SDRAM Operations ...
Page 45
... V the V specified range. 2. Although not required by the Micron device, JEDEC specifies issuing another LMR command ( prior to activating any bank. If another LMR command is issued, the same, previ- ously issued operating parameters must be used. 3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LMR com- mand at Ta0 ...
Page 46
... Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations Burst Length Reserved Reserved Reserved Reserved Reserved CAS Latency Reserved Reserved 2 3 (-5B only) ...
Page 47
... A0 – 0-1-2-3-4-5-6 1-2-3-4-5-6-7 2-3-4-5-6-7-0 3-4-5-6-7-0-1 4-5-6-7-0-1-2 5-6-7-0-1-2-3 6-7-0-1-2-3-4 7-0-1-2-3-4-5-6 47 1Gb: x4, x8, x16 DDR SDRAM Type = Interleaved – 0-1 1-0 – 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 – 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations ...
Page 48
... READ NOP NOP READ NOP NOP Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 1Gb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n NOP T2n T3 T3n NOP T3 T3n NOP Don’t Care ...
Page 49
... A[6:0] set to the desired values. A DLL reset is initiated by issuing an LMR command with bits A7 and A[n:9] each set to zero, bit A8 set to one, and bits A[6:0] set to the desired values. Although not required by the Micron device, JEDEC specifications recommend that an LMR command resetting the DLL should always be followed by an LMR command selecting normal operating mode ...
Page 50
... E0 0 Enable 1 Disable Drive Strength E1 0 Normal 1 Reduced E1, E0 Operating Mode Valid Reserved – Reserved t RCD (MIN) should be divided by Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations t RRD; the t RC. ...
Page 51
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev RCD ( RRD) MIN When 2 < ACT NOP Row Bank y t RRD t Micron Technology, Inc., reserves the right to change products or specifications without notice. 51 1Gb: x4, x8, x16 DDR SDRAM RCD ( RRD) MIN RD/WR NOP NOP ...
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... PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN 1Gb: x4, x8, x16 DDR SDRAM t DQSS (NOM) case is shown; the t DQSS [MIN] and Micron Technology, Inc., reserves the right to change products or specifications without notice. 52 Operations t DQSS [MAX] are t RAS ©2000 Micron Technology, Inc. All rights reserved. ...
Page 53
... NOP NOP NOP AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 53 1Gb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 NOP NOP T3n T4 T5 NOP NOP T3n T4 T4n T5 NOP ...
Page 54
... NOP READ NOP Bank, Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 54 1Gb: x4, x8, x16 DDR SDRAM Operations T3n T4 T4n T5 T5n NOP NOP DO b T3n T4 T4n T5 T5n NOP ...
Page 55
... NOP NOP DO b T3n T4 T5 T5n NOP NOP DO T3n T4 T4n T5 NOP NOP Transitioning Data Don’t Care t DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 NOP T6 NOP b T6 NOP DO b ...
Page 56
... READ READ READ Bank, Bank, Bank, Col x Col b Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 56 1Gb: x4, x8, x16 DDR SDRAM Operations T4 T4n T5 T5n NOP NOP ...
Page 57
... BST 1 NOP NOP AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 57 1Gb: x4, x8, x16 DDR SDRAM Operations T4 T5 NOP NOP T4 T5 NOP NOP T3n T4 T5 NOP NOP Transitioning Data Don’ ...
Page 58
... BST NOP NOP AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 58 1Gb: x4, x8, x16 DDR SDRAM Operations T4 T4n T5 T5n NOP NOP DI b T3n T4 T5 T5n WRITE NOP Bank, ...
Page 59
... RAS (MIN) is met, a READ command with auto precharge enabled would cause AC, DQSCK, and DQSQ. t RAS (MIN) is met. Micron Technology, Inc., reserves the right to change products or specifications without notice. 59 1Gb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 NOP ACT Bank a, ...
Page 60
... Bank RCD t RAS RPRE t LZ (MIN (MIN) Micron Technology, Inc., reserves the right to change products or specifications without notice. 60 1Gb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n PRE NOP NOP All banks One bank 5 ...
Page 61
... Data Data valid valid valid window window window t DQSQ window. DQS transitions at T2 and Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations DQSQ T3n T3n T3n ...
Page 62
... T3n T2n T3 T3n T2n T3 T3n Data valid Data valid Data valid window window window t DQSQ window. LDQS defines the lower DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations ...
Page 63
... T3 T3n (MAX (MAX) t DQSQ window time); if auto precharge is not Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T5n (MAX) t RPST T5n T5n T5n t DQSS for ...
Page 64
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev WTR should be met, as shown in Figure period are written to the internal array; any subsequent data-in Micron Technology, Inc., reserves the right to change products or specifications without notice. 64 1Gb: x4, x8, x16 DDR SDRAM Operations t WTR period are written ...
Page 65
... DM t DQSS DQS DQSS DQS Transitioning Data 65 1Gb: x4, x8, x16 DDR SDRAM T2 T2n T3 NOP NOP Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations ...
Page 66
... WRITE Bank, Col n t DQSS 1Gb: x4, x8, x16 DDR SDRAM T3 T3n T4 T4n T5 NOP NOP NOP DI n Transitioning Data Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations ...
Page 67
... Col a Col Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T4n T5 T5n NOP Don’t Care T5 T5n NOP Don’t Care ...
Page 68
... T4 T5 READ NOP Bank a, Col Transitioning Data t WTR is not required, and the READ Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 T6n NOP Don’t Care ...
Page 69
... DDR SDRAM T3n T4 T5 T5n NOP NOP Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 T6n NOP Don’t Care ...
Page 70
... DDR SDRAM T5n T3n T4 T5 NOP NOP Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 T6n NOP Don’t Care ...
Page 71
... DDR SDRAM T4 T5 PRE NOP Bank all) Transitioning Data not required, and Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’t Care ...
Page 72
... 1Gb: x4, x8, x16 DDR SDRAM T3n T4 T4n T5 NOP PRE t RP Bank all) Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’t Care ...
Page 73
... 1Gb: x4, x8, x16 DDR SDRAM T3n T4 T4n T5 PRE NOP t RP Bank all) Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’t Care ...
Page 74
... Bank x t RCD t RAS t DQSS (NOM WPRES WPRE Micron Technology, Inc., reserves the right to change products or specifications without notice. 74 1Gb: x4, x8, x16 DDR SDRAM T5 T5n T6 T7 NOP 1 NOP 1 NOP DQSL DQSH WPST Transitioning Data © ...
Page 75
... NOP NOP NOP DQSL t DQSH t WPST Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T8 1 PRE All banks One bank 4 Bank Don’t Care ...
Page 76
... WPRE t DQSL t DQSH Transitioning Data t DQSS (MIN). t DQSS (MAX). Micron Technology, Inc., reserves the right to change products or specifications without notice. 76 1Gb: x4, x8, x16 DDR SDRAM Operations T2n T3 t DSS 3 t WPST Don’t Care t RP) after the t RAS (MIN), as described for t RP) is completed ...
Page 77
... Bank x t RCD, t RAP RAS RPRE t LZ (MIN (MIN) t RAS has been satisfied. Micron Technology, Inc., reserves the right to change products or specifications without notice. 77 1Gb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n NOP NOP ...
Page 78
... NOP NOP NOP DQSL t DQSH t WPST Transitioning Data t REFI (MAX). t Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations T8 1 NOP t RP Don’t Care REFI; Micron t AC between ...
Page 79
... RP t RFC voltage is also required for the full duration of SELF REF Micron Technology, Inc., reserves the right to change products or specifications without notice. 79 1Gb: x4, x8, x16 DDR SDRAM Operations t RFC later. Ta1 Tb0 Tb1 Tb2 ( ( ) ) ( ...
Page 80
... REFI interval while Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Operations Tc1 ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ...
Page 81
... NOP or DESELECT command). A valid executable command may be applied one clock cycle later. PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN 1Gb: x4, x8, x16 DDR SDRAM t REFC). Micron Technology, Inc., reserves the right to change products or specifications without notice. 81 Operations ©2000 Micron Technology, Inc. All rights reserved. ...
Page 82
... Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur ...