MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 47

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

Burst Length (BL)
Burst Type
Table 28:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Burst Length
2
4
8
Burst Definition
Starting Column Address
A2
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length
being programmable for both READ and WRITE bursts, as shown in Figure 21 on
page 46. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command. BL = 2, BL = 4, or BL = 8 locations
are available for both the sequential and the interleaved burst types. Reserved states
should not be used, as unknown operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block—
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[i:1] when BL = 2, by A[i:2] when BL = 4, and by A[i:3] when BL = 8
(where Ai is the most significant column address bit for a given configuration). The
remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. For example: for BL = 8, A[i:3]select the eight-data-element block;
A[2:0] select the first access within the block.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 28.
A1
A1
–
–
–
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
47
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
–
–
–
Order of Accesses Within a Burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR SDRAM
Type = Interleaved
©2000 Micron Technology, Inc. All rights reserved.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
–
–
–
Operations