MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 63

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

Figure 35:
WRITE
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
All DQ values collectively 4
DQS or LDQS/UDQS 3
DQ (first data valid)
DQ (last data valid)
Data Output Timing –
Notes:
Note:
CK#
CK
1. READ command with CL = 2 issued at T0.
2.
3. DQ transitioning after DQS transition define the
4. All DQ must transition by
5.
6.
7.
During a WRITE command, the value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst (after
selected, the row will remain open for subsequent accesses.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS
(
All of the WRITE diagrams show the nominal case, and where the two extreme cases
(that is,
included. Figure 36 on page 65 shows the nominal case and the extremes of
BL = 4. Upon completion of a burst, assuming no other commands have been initiated,
the DQ will remain High-Z and any additional input data will be ignored.
t
DQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle).
For the WRITE commands used in the following illustrations, auto precharge is dis-
abled.
t
DQS skew.
t
t
t
DQSCK is the DQS output window relative to CK and is the “long term” component of the
AC is the DQ output window relative to CK and is the “long term” component of DQ skew.
LZ (MIN) and
HZ (MAX) and
t LZ (MIN)
T0 1
t
DQSS [MIN] and
t
T1
AC and
t
AC (MIN) are the first valid signal transitions.
t LZ (MIN)
t
AC (MAX) are the latest valid signal transitions.
t RPRE
t
DQSCK
t
T2
DQSS [MAX]) might not be intuitive; they have also been
t DQSCK 2 (MIN)
t
t DQSCK 2 (MAX)
DQSQ after DQS transitions, regardless of
T2
T2
63
T2
T2n
T2n
T2n
T2n
t AC 5 (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
T3
T3
T3n
t
t
WR time); if auto precharge is not
T3n
DQSQ window.
T3n
T3n
t AC 5 (MAX)
1Gb: x4, x8, x16 DDR SDRAM
T4
T4
T4
T4
T4n
t DQSCK 2 (MAX)
t DQSCK 2 (MIN)
T4n
©2000 Micron Technology, Inc. All rights reserved.
T4n
T4n
T5
t
AC.
T5
T5
T5
t HZ (MAX)
T5n
t HZ (MAX)
Operations
t RPST
T5n
T5n
t
T5n
DQSS for
T6