MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 77

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

Figure 49:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Case 1: t AC (MIN) and t DQSCK (MIN)
Case 2: t AC (MAX) and t DQSCK (MAX)
Command
BA0, BA1
Address
DQ
DQ
DQS
DQS
CK#
CKE
A10
DM
CK
6
6
Bank READ – with Auto Precharge
t IS
t IS
NOP
T0
t IH
1
t IH
Notes:
Bank x
IS
t IS
Row
ACT
Row
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. The READ command can only be applied at T3 if
4. Enable auto precharge.
5.
6. DO n = data-out from column n; subsequent elements are provided in the programmed
7. Refer to Figure 33 on page 61, Figure 34 on page 62, and Figure 35 on page 63 for detailed
T1
t IH
IH
times.
t
order.
DQS and DQ timing.
t CK
RP starts only after
t RCD, t RAP 3
t RAS
t RC
NOP
T2
1
t CH
t CL
READ
t IS
Bank x
4
Col n
t
T3
RAS has been satisfied.
t IH
2,3
t LZ (MIN)
CL = 2
77
NOP
T4
t RPRE
1
t LZ (MIN)
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t RPRE
NOP
T5
t DQSCK (MIN)
DO
t DQSCK (MAX)
1
n
t AC (MIN)
DO
t
t AC (MAX)
n
RAP is satisfied at T3.
T5n
1Gb: x4, x8, x16 DDR SDRAM
t RP 5
NOP
T6
1
Transitioning Data
t HZ (MAX)
T6n
t RPST
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t RPST
NOP
T7
1
Operations
Don’t Care
Bank x
ACT
Row
T8
Row