MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 31

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
44.
45. During initialization, V
46. The current Micron part operates below 83 MHz (slowest specified JEDEC operating
47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
48. Random address is changing; 50% of data is changing at every transfer.
49. Random address is changing; 100% of data is changing at every transfer.
50. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
51. I
52. Whenever the operating frequency is altered, not including jitter, the DLL is required
53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz.
54. The -6T speed grade will operate with
55. DRAM devices should be evenly addressed when being accessed. Disproportionate
t
but specify when the device output is no longer driving (
(
Alternatively, V
provided a minimum of 42: of series resistance is used between the V
the input pin.
frequency). As such, future die may not reflect this option.
LOW.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until
I
remain stable. Although I
to be reset followed by 200 clock cycles before any READ command.
Any noise above 20 MHz at the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV.
at any slower frequency.
accesses to a particular row address may result in reduction of the product lifetime.
RPST end point and
t
DD2N
DD2Q
RPRE).
specifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
is similar to I
TT
may be 1.35V maximum during power-up, even if V
DD2F
t
RPRE begin point are not referenced to a specific voltage level
DDQ
except I
DD2F
31
, V
TT
, I
DD2N
, and V
DD2Q
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, and I
t
Electrical Specifications – DC and AC
RFC has been satisfied.
specifies the address and control inputs to
t
REF
RAS (MIN) = 40ns and
must be equal to or less than V
DD2Q
1Gb: x4, x8, x16 DDR SDRAM
are similar, I
t
RPST) or begins driving
©2000 Micron Technology, Inc. All rights reserved.
DD2F
t
RAS (MAX) = 120,000ns
is “worst case.”
DD
TT
/V
supply and
DD
DDQ
+ 0.3V.
are 0V,