MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 52

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 29 on page 57. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 30 on page 58. The
t
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 31 on page 59. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both
and
last data elements.
DQSS (MAX) case has a longer bus idle time. (
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RP have been met. Part of the row precharge time is hidden during the access of the
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSS [MIN] and
1Gb: x4, x8, x16 DDR SDRAM
t
DQSS (NOM) case is shown; the
©2000 Micron Technology, Inc. All rights reserved.
t
DQSS [MAX] are
Operations
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RAS