MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 36

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

Table 25:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Current State
Any
Idle
Row activating, active,
or precharging
Read (auto precharge
disabled)
Write (auto precharge
disabled)
Read (with auto-
precharge)
Write (with auto-
precharge)
Truth Table 4 – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table; Notes appear on page 36
Notes:
CS#
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
1. This table applies when CKE
valid state for precharging.
bank.
precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
after
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when
• Accessing mode register: Starts with registration of an LMR command and ends when
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
RAS# CAS#
is met. After
t
state.
t
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
MRD has been met. After
RP is met. After
t
XSNR has been met (if the previous state was self refresh).
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
t
RFC is met, the DDR SDRAM will be in the all banks idle state.
WE#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
t
RP is met, all banks will be in the idle state.
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
n-1
36
t
was HIGH and CKE
MRD is met, the DDR SDRAM will be in the all banks idle
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
1Gb: x4, x8, x16 DDR SDRAM
is HIGH (see Table 27 on page 38) and
©2000 Micron Technology, Inc. All rights reserved.
Commands
Notes
7, 9
7, 8
7, 9
7
7
7
7
7
7
7
t
RFC