MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 26

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

Notes
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
10. The value of V
11. I
12. Enables on-chip refresh and address counters.
13. I
14. This parameter is sampled. V
15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is
1. All voltages referenced to V
2. Tests for AC timing, I
3. Outputs (except for I
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_2 standard (that
6. All speed grades are not offered on all densities. Refer to page 1 for availability.
7. V
8. V
9. V
at nominal reference/supply voltage levels, but the related specifications and the
device operation are guaranteed for the full voltage range specified.
ment, but input timing is still referenced to V
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1 V/ns in the range between V
is, the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
the DC level of the same. Peak-to-peak noise (noncommon mode) on V
exceed ±2% of the DC value. Thus, from V
and an additional ±25mV for AC noise. This measurement is to be taken at the nearest
V
resistors, it is expected to be set equal to V
level of V
level on CK#.
must track variations in the DC level of the same.
with minimum cycle times at CL = 3 for -5B; CL = 2.5, -6T/-75 speeds with the outputs
open.
the defined cycle rate.
f = 100 MHz, T
grouped with I/O pins, reflecting the fact that they are matched in loading.
less than 0.5 V/ns, timing must be derated:
100 mV/ns reduction in slew rate from the 500 mV/ns.
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -5B
and -6T, slew rates must be greater than or equal to 0.5 V/ns.
Output
(V
DD
DD
REF
REF
TT
ID
OUT
is the magnitude of the difference between the input level on CK and the input
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized and is averaged at
is not applied directly to the device. V
)
is expected to equal V
bypass capacitor.
V
REF
TT
50:
30pF
.
Reference
point
IX
A
DD
= 25°C, V
and V
tests may use a V
DD
DD
MP
, and electrical AC and DC characteristics may be conducted
measurements) measured with equivalent load:
OUT(DC)
is expected to equal V
DDQ
26
SS
.
DD
/2 of the transmitting device and to track variations in
= 2.5V ±0.2V, V
= V
IL
DDQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-to-V
Electrical Specifications – DC and AC
IL(AC)
/2, V
DDQ
TT
REF
IH
t
IS has an additional 50ps per each
is a system supply for signal termination
REF
and V
, and it must track variations in the DC
OUT
swing of up to 1.5V in the test environ-
/2, V
DDQ
DDQ
1Gb: x4, x8, x16 DDR SDRAM
(or to the crossing point for CK/CK#),
(peak-to-peak) = 0.2V. DM input is
IH(AC)
REF
/2 of the transmitting device and
= 2.5V ±0.2V, V
is allowed ±25mV for DC error
t
IH has 0ps added, that is, it
.
©2000 Micron Technology, Inc. All rights reserved.
REF
= V
REF
SS
,
may not