MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 64

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 37 on page 66 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 38 on page 67. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 39 on page 67.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst,
on page 68.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 41 on page 69.
Note that only the data-in pairs that are registered prior to the
to the internal array, and any subsequent data-in should be masked with DM, as shown
in Figure 42 on page 70.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst,
Figure 43 on page 71.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 44 on page 72 and Figure 45 on page 73. Only the data-in pairs regis-
tered prior to the
should be masked with DM, as shown in Figures 44 and 45. After the PRECHARGE
command, a subsequent command to the same bank cannot be issued until
t
WR period are written to the internal array; any subsequent data-in
64
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t
WTR should be met, as shown in Figure 40
1Gb: x4, x8, x16 DDR SDRAM
t
WR should be met, as shown in
©2000 Micron Technology, Inc. All rights reserved.
t
WTR period are written
Operations
t
RP is met.