MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 45

• Manufacturer Part Number: MT46V64M16P-6T IT:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron

Figure 20:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Command
BA0, BA1
Address
V
V
DQS
DD
V
CK#
CKE
A10
V
DM
DQ
CK
TT
REF
DD
Q
1
t VTD 1
INITIALIZATION Timing Diagram
Notes:
LVCMOS
LOW level
Power-up: V
T = 200µs
1. V
2. Although not required by the Micron device, JEDEC specifies issuing another LMR command
3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LMR com-
4.
5. While programming the operating parameters, reset the DLL with A8 = 1.
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V
even if V
the V
specified range.
(A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previ-
ously issued operating parameters must be used.
mand at Ta0.
t
DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be
issued.
MRD is required before any command can be applied (during MRD time only NOPs or
DD
TT
TT
t IS t IH
t IS
and CK stable
NOP
, and V
T0
is not applied directly to the device; however,
High-Z
High-Z
TT
t IH
t CH
t CK
supply and the input pin. Once initialized, V
DD
REF
/V
t CL
All banks
DDQ
t IS t IH
d V
PRE
T1
DD
are 0V, provided a minimum of 42: of series resistance is used between
+ 0.3V. Alternatively, V
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t RP
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Load extended
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t IS t IH
t IS t IH
t IS t IH
BA0 = 1
BA1 = 0
Code
Code
LMR
Ta0
45
t MRD
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Load mode
register5
Code 3
BA0 = 0
BA1 = 0
Code
LMR
Tb0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t MRD
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may be 1.35V maximum during power-up,
All banks
t IS t IH
PRE
Tc0
t
VTD t 0 to avoid device latch-up. V
1Gb: x4, x8, x16 DDR SDRAM
REF
t RP
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must always be powered within the
200 cycles of CK4
Td0
AR
Indicates A Break in
Time Scale
©2000 Micron Technology, Inc. All rights reserved.
t RFC
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Te0
AR
t RFC
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Operations
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ACT 2
Don’t Care
Tf0
BA
RA
RA
DDQ
,