MT46V64M16P-6T IT:A Micron, MT46V64M16P-6T IT:A Datasheet - Page 60

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MT46V64M16P-6T IT:A

Manufacturer Part Number
MT46V64M16P-6T IT:A
Description
DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
Manufacturer
Micron
Datasheet
Figure 32:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. J; Core DDR Rev. E 7/11 EN
Command
BA0, BA1
Case 1:
Case 2:
Address
DQS
DQS
CK#
CKE
A10
DM
DQ
DQ
CK
t
t
AC (MIN) and
AC (MAX) and
Bank READ – Without Auto Precharge
t
t
IS
NOP
IS
T0
t
1
Notes:
t
IH
t
IH
DQSCK (MIN)
t
DQSCK (MAX)
t
t
Bank x
IS
IS
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
7. Refer to Figure 33 on page 61, Figure 34 on page 62, and Figure 35 on page 63 for detailed
Row
Row
ACT
T1
t
t
times.
the programmed order.
DQS and DQ timing.
IH
IH
t
CK
t
t RAS 3
t
RCD
RC
NOP
T2
1
t
CH
t
CL
t
Bank x
READ
4
Col n
IS
T3
2
t
t
IH
LZ (MIN)
CL = 2
60
NOP
T4
t
1
RPRE
t
LZ (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RPRE
One bank
All banks
Bank x
PRE
T5
t
3
DO
t
DQSCK (MIN)
n
DQSCK (MAX)
5
t
AC (MIN)
DO
t
n
AC (MAX)
T5n
1Gb: x4, x8, x16 DDR SDRAM
t
RP
NOP
t
RAS (MIN) is met.
T6
1
Transitioning Data
t
HZ (MAX)
T6n
t
RPST
©2000 Micron Technology, Inc. All rights reserved.
t
RPST
NOP
T7
1
Operations
Bank x
Don’t Care
Row
Row
ACT
T8

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