S9S12G96F0CLL Freescale Semiconductor, S9S12G96F0CLL Datasheet - Page 186

• Manufacturer Part Number: S9S12G96F0CLL
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0CLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

1
2
3
4
Port Integration Module (S12GPIMV1)
188
Port
AD
Available in group
Refer to device memory map to determine related module.
Read always returns logic level on pins.
Routing takes only effect if the PKGCR is set to 20 TSSOP.
J
Address
0x026C
0x026D
0x027C
0x027D
0x026A
0x026B
0x026E
0x026F
0x027A
0x027B
0x027E
0x027F
0x0260
0x0261
0x0262
0x0266
0x0268
0x0269
0x0270
0x0271
0x0272
0x0273
0x0274
0x0275
0x0276
0x0277
0x0278
0x0279
Global
:
G1
Reserved for ACMP available in group
Reserved
PTJ—Port J Data Register
PTIJ—Port J Input Register
DDRJ—Port J Data Direction Register
Reserved
PERJ—Port J Pull Device Enable Register
PPSJ—Port J Polarity Select Register
PIEJ—Port J Interrupt Enable Register
PIFJ—Port J Interrupt Flag Register
PT0AD—Port AD Data Register
PT1AD—Port AD Data Register
PTI0AD—Port AD Input Register
PTI1AD—Port AD Input Register
DDR0AD—Port AD Data Direction Register
DDR1AD—Port AD Data Direction Register
Reserved for RVACTL on G(A)240 and G(A)192 only
PRR1—Pin Routing Register 1
PER0AD—Port AD Pull Device Enable Register
PER1AD—Port AD Pull Device Enable Register
PPS0AD—Port AD Polarity Select Register
PPS1AD—Port AD Polarity Select Register
PIE0AD—Port AD Interrupt Enable Register
PIE1AD—Port AD Interrupt Enable Register
PIF0AD—Port AD Interrupt Flag Register
PIF1AD—Port AD Interrupt Flag Register
only. In any other case this address is reserved.
Table 2-18. Block Memory Map (0x0000-0x027F) (continued)
MC9S12G Family Reference Manual,
Register
6
G2
and
G3
Rev.1.23
Access
R(/W)
R(/W)
R(/W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
0xFF (G1,G2)
Reset Value
0x0F (G3)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
3
3
3
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Section/Page
(ACMP)
(ACMP)
(RVA)