S9S12G96F0CLL Freescale Semiconductor, S9S12G96F0CLL Datasheet - Page 259

• Manufacturer Part Number: S9S12G96F0CLL
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0CLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

3.7
The ACMP compares two analog input voltages applied to ACMPM and ACMPP. The comparator output
is high when the voltage at the non-inverting input is greater than the voltage at the inverting input, and is
low when the non-inverting input voltage is lower than the inverting input voltage.
The ACMP is enabled with register bit ACMPC[ACE]. When ACMPC[ACE] is set, the input pins are
connected to low-pass filters. The comparator output is disconnected from the subsequent logic, which is
held at its state for 63 bus clock cycles after setting ACMPC[ACE] to “1” to mask potential glitches. This
initialization delay must be accounted for before the first comparison result can be expected.
The initial hold state after reset is zero, thus if input voltages are set to result in “true” result
(V
Similarly the flag will also be set when disabling the ACMP, then re-enabling it with the inputs changing
to produce an opposite result to the hold state before the end of the initialization delay.
By setting the ACMPC[ACICE] bit the gated comparator output can be connected to the synchronized
timer input capture channel 5 (see
interrupts on ACMP events.
The comparator output signal synchronized to the bus clock is used to read the comparator output status
(ACMPS[ACO]) and to set the interrupt flag (ACMPS[ACIF]).
The condition causing the interrupt flag (ACMPS[ACIF]) to assert is selected with register bits
ACMPC[ACMOD1:ACMOD0]. This includes any edge configuration, that is rising, or falling, or rising
and falling (toggle) edges of the comparator output. Also flag setting can be disabled.
An interrupt will be generated if the interrupt enable bit (ACMPC[ACIE]) and the interrupt flag
(ACMPS[ACIF]) are both set. ACMPS[ACIF] is cleared by writing a 1.
The raw comparator output signal ACMPO can be driven out on an external pin by setting the
ACMPC[ACOPE] bit.
Freescale Semiconductor
Field
ACIF
ACO
ACMPP
7
6
Functional Description
> V
ACMP Interrupt Flag—
ACIF is set when a compare event occurs. Compare events are defined by ACMOD[1:0]. Writing a logic “1” to the
bit field clears the flag.
0 Compare event has not occurred
1 Compare event has occurred
ACMP Output—
Reading ACO returns the current value of the synchronized ACMP output. Refer to ACE description to account for
initialization delay on this path.
ACMPM
) before the initialization delay has passed, a flag will be set immediately after this.
Table 3-3. ACMPS Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
Figure
3-1). This feature can be used to generate time stamps and timer
Description
5V Analog Comparator (ACMPV1)
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