S9S12G96F0CLL Freescale Semiconductor, S9S12G96F0CLL Datasheet - Page 369

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S9S12G96F0CLL

Manufacturer Part Number
S9S12G96F0CLL
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G96F0CLL

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT

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Addres
0x003C
0x003D
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
0x003A
0x003B
0x003E
0x003F
0x02F0
0x02F1
0x02F2
s
10.3
This section provides a detailed description of all registers accessible in the S12CPMU.
10.3.1
The S12CPMU registers are shown in
Freescale Semiconductor
RESERVEDCP
RESERVEDCP
CPMUCLKS
RESERVED
CPMUCOP
CPMUFLG
CPMUPLL
MUTEST0
MUTEST1
CPMUINT
CPMURTI
POSTDIV
ARMCOP
REFDIV
APICTL
LVCTL
CPMU
CPMU
CPMU
CPMU
CPMU
CPMU
SYNR
Name
Memory Map and Registers
Module Memory Map
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PLLSEL
APICLK
RTDEC
WCOP
RTIE
Bit 7
RTIF
Bit 7
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
0
0
0
Figure 10-3. CPMU Register Summary
MC9S12G Family Reference Manual, Rev.1.23
= Unimplemented or Reserved
RSBCK
PORF
PSTP
RTR6
Bit 6
6
0
0
0
0
0
0
0
0
0
Figure
WRTMASK
10-3.
RTR5
LVRF
FM1
Bit 5
5
0
0
0
0
0
0
0
0
0
0
0
OSCSEL1
LOCKIF
LOCKIE
APIES
RTR4
COP
FM0
Bit 4
4
0
0
0
0
0
0
0
S12 Clock, Reset and Power Management Unit (S12CPMU)
APIEA
LOCK
RTR3
PRE
Bit 3
3
0
0
0
0
0
0
0
0
SYNDIV[5:0]
POSTDIV[4:0]
APIFE
RTR2
LVDS
ILAF
PCE
CR2
Bit 2
2
0
0
0
0
0
0
REFDIV[3:0]
OSCSEL
OSCIE
OSCIF
RTR1
APIE
LVIE
CR1
Bit 1
RTI
1
0
0
0
0
0
OSCSEL0
UPOSC
RTR0
Bit 0
COP
APIF
CR0
Bit 0
LVIF
0
0
0
0
0
0
371

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