S9S12G96F0CLL Freescale Semiconductor, S9S12G96F0CLL Datasheet - Page 411

• Manufacturer Part Number: S9S12G96F0CLL
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0CLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

generates a Clock Monitor Reset.In Full Stop Mode the external oscillator and the clock monitor are
disabled.
10.5.2.2
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus COP reset is generated.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit.
In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the
COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0.
In Pseudo Stop Mode and Full Stop Mode with COPOSCSEL1=1 the COP continues to run.
Table 10-28.gives an overview of the COP condition (run, static) in Stop Mode depending on legal
configuration and status bit settings:
Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP
register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the
program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55
or $AA is written, a COP reset is generated.
Freescale Semiconductor
COPOSCSEL1
1
0
0
0
0
0
0
0
0
0
0
0
0
Computer Operating Properly Watchdog (COP) Reset
PSTP
x
1
1
1
1
1
0
0
0
0
0
0
0
Table 10-28. COP condition (run, static) in Stop Mode
PCE
x
1
1
1
0
0
1
1
1
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.23
COPOSCSEL0
x
1
0
0
0
1
1
0
0
1
0
0
0
OSCE
1
0
1
1
1
1
0
1
1
1
0
x
x
S12 Clock, Reset and Power Management Unit (S12CPMU)
UPOSC
1
1
1
0
1
1
0
0
x
x
x
x
x
COP counter behavior in Stop Mode
Static (OSCCLK)
Static (OSCCLK)
Satic (OSCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Run (OSCCLK)
(clock source)
Run (ACLK)
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