S9S12G96F0CLL Freescale Semiconductor, S9S12G96F0CLL Datasheet - Page 331

• Manufacturer Part Number: S9S12G96F0CLL
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0CLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT

8.4.1
Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data
in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main
blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor
address bus activity. Comparator A can also be configured to monitor databus activity and mask out
individual data bus bits during a compare. Comparators can be configured to use R/W and word/byte
access qualification in the comparison. A match with a comparator register value can initiate a state
sequencer transition to another state (see
a forced match, a state sequencer transition can occur immediately on a successful match of system busses
and comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only
if the instruction reaches the execution stage of the instruction queue can a state sequencer transition occur.
In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated.
A state sequencer transition to final state (with associated breakpoint, if enabled) can be initiated by
writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and must be read out using
standard 16-bit word reads.
8.4.2
The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with
the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares
the data buses to the data stored in DBGADH, DBGADL and allows masking of individual data bus bits.
Freescale Semiconductor
TAGHITS
SECURE
CPU BUS
READ TRACE DATA (DBG READ DATA BUS)
S12SDBG Operation
Comparator Modes
COMPARATOR A
COMPARATOR C
COMPARATOR B
MC9S12G Family Reference Manual, Rev.1.23
Figure 8-23. DBG Overview
Figure
8-24). Either forced or tagged matches are possible. Using
MATCH1
MATCH0
MATCH2
CONTROL
MATCH
LOGIC
TAG &
TRANSITION
STATE
BREAKPOINT REQUESTS
S12S Debug Module (S12SDBGV2)
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
STATE
TRACE
CONTROL
TRIGGER
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