LPC11U35FHI33/501, NXP Semiconductors, LPC11U35FHI33/501, Datasheet
LPC11U35FHI33/501,
Specifications of LPC11U35FHI33/501,
Related parts for LPC11U35FHI33/501,
LPC11U35FHI33/501, Summary of contents
Page 1
LPC11U3x 32-bit ARM Cortex-M0 microcontroller 128 kB flash SRAM and 4 kB EEPROM; USB device; USART Rev. 1 — 20 April 2012 1. General description The LPC11U3x are a ARM Cortex-M0 based, low-cost 32-bit ...
Page 2
... NXP Semiconductors Serial Wire Debug. Digital peripherals: General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode. GPIO pins can be selected as edge and level sensitive interrupt sources. Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. ...
Page 3
... NXP Semiconductors Unique device serial number for identification. Single 3.3 V power supply (1 3.6 V). Temperature range −40 °C to +85 °C. Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages. 3. Applications Consumer peripherals Medical Industrial control 4. Ordering information Table 1. ...
Page 4
... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash in kB LPC11U34FHN33/311 40 LPC11U34FBD48/311 40 LPC11U34FHN33/421 48 LPC11U34FBD48/421 48 LPC11U35FHN33/401 64 LPC11U35FBD48/401 64 LPC11U35FBD64/401 64 LPC11U35FHI33/501 64 LPC11U35FET48/501 64 LPC11U36FBD48/401 96 LPC11U36FBD64/401 96 LPC11U37FBD48/401 128 LPC11U37FBD64/501 128 LPC11U3X Product data sheet EEPROM SRAM USART ...
Page 5
... NXP Semiconductors 5. Block diagram LPC11U3x HIGH-SPEED GPIO ports 0/1 GPIO RXD TXD (1) (1) DCD, DSR , RI SMARTCARD INTERFACE CTS, RTS, DTR SCLK CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 (2) CT16B0_CAP[1:0] CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 (2) CT16B1_CAP[1:0] CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 (2) CT32B0_CAP[1:0] CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 (2) CT32B1_CAP[1:0] WINDOWED WATCHDOG ...
Page 6
... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO1_19/DTR/SSEL1 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 For parts LPC11U34FHN33/311, LPC11U34FHN33/421, LPC11U35FHN33/401, LPC11U35FHI33/501 Fig 2. Pin configuration (HVQFN33) LPC11U3X Product data sheet terminal 1 index area 1 2 RESET/PIO0_0 3 XTALIN 4 XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. ...
Page 7
... NXP Semiconductors Fig 3. LPC11U3X Product data sheet ball A1 index area Pin configuration (TFBGA48) All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 April 2012 LPC11U3x 32-bit ARM Cortex-M0 microcontroller LPC11U35FET48/501 002aag810 Transparent top view © ...
Page 8
... NXP Semiconductors PIO1_25/CT32B0_MAT1 PIO1_19/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO1_26/CT32B0_MAT2/RXD PIO1_27/CT32B0_MAT3/TXD Fig 4. Pin configuration (LQFP48) LPC11U3X Product data sheet LPC11U34FBD48/311 LPC11U34FBD48/421 XTALIN 6 LPC11U35FBD48/401 LPC11U36FBD48/401 XTALOUT 7 LPC11U37FBD48/401 All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 April 2012 ...
Page 9
... NXP Semiconductors PIO1_0 1 PIO1_25 2 3 PIO1_19 4 RESET/PIO0_0 PIO0_1 5 PIO1_7 XTALIN 9 XTALOUT PIO0_20 11 PIO1_10 12 PIO0_2 13 14 PIO1_26 15 PIO1_27 PIO1_4 16 See Table 3 for the full pin name. Fig 5. Pin configuration (LQFP64) LPC11U3X Product data sheet LPC11U35FBD64/401 LPC11U36FBD64/401 LPC11U37FBD64/501 All information provided in this document is subject to legal disclaimers. ...
Page 10
... NXP Semiconductors 6.2 Pin description Table 3 port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and PIO0_5. Every port pin has a corresponding IOCON register for programming the digital or analog function, the pull-up/pull-down configuration, the repeater, and the open-drain modes ...
Page 11
... NXP Semiconductors Table 3. Pin description Symbol PIO0_6/USB_CONNECT/ 15 SCK0 PIO0_7/CTS 16 PIO0_8/MISO0/ 17 CT16B0_MAT0 PIO0_9/MOSI0/ 18 CT16B0_MAT1 SWCLK/PIO0_10/SCK0/ 19 CT16B0_MAT2 TDI/PIO0_11/AD0/ 21 CT32B0_MAT3 TMS/PIO0_12/AD1/ 22 CT32B1_CAP0 TDO/PIO0_13/AD2/ 23 CT32B1_MAT0 TRST/PIO0_14/AD3/ 24 CT32B1_MAT1 SWDIO/PIO0_15/AD4/ 25 CT32B1_MAT2 LPC11U3X Product data sheet Reset Type Description state [ I [3] ...
Page 12
... NXP Semiconductors Table 3. Pin description Symbol PIO0_16/AD5/ 26 CT32B1_MAT3/WAKEUP PIO0_17/RTS/ 30 CT32B0_CAP0/SCLK PIO0_18/RXD/ 31 CT32B0_MAT0 PIO0_19/TXD/ 32 CT32B0_MAT1 PIO0_20/CT16B1_CAP0 7 PIO0_21/CT16B1_MAT0/ 12 MOSI1 PIO0_22/AD6/ 20 CT16B1_MAT1/MISO1 PIO0_23/AD7 27 PIO1_0/CT32B1_MAT0 - PIO1_1/CT32B1_MAT1 - PIO1_2/CT32B1_MAT2 - LPC11U3X Product data sheet Reset Type Description state [ I/O [3] B3 ...
Page 13
... NXP Semiconductors Table 3. Pin description Symbol PIO1_3/CT32B1_MAT3 - PIO1_4/CT32B1_CAP0 - PIO1_5/CT32B1_CAP1 - PIO1_6 - PIO1_7 - PIO1_8 - PIO1_9 - PIO1_10 - PIO1_11 - PIO1_12 - PIO1_13/DTR/ - CT16B0_MAT0/TXD PIO1_14/DSR/ - CT16B0_MAT1/RXD PIO1_15/DCD/ 28 CT16B0_MAT2/SCK1 PIO1_16/RI/ - CT16B0_CAP0 PIO1_17/CT16B0_CAP1/ - RXD PIO1_18/CT16B1_CAP1/ - TXD PIO1_19/DTR/SSEL1 1 LPC11U3X Product data sheet Reset Type Description state [ ...
Page 14
... NXP Semiconductors Table 3. Pin description Symbol PIO1_20/DSR/SCK1 - PIO1_21/DCD/MISO1 - PIO1_22/RI/MOSI1 - PIO1_23/CT16B1_MAT1/ - SSEL1 PIO1_24/CT32B0_MAT0 - PIO1_25/CT32B0_MAT1 - PIO1_26/CT32B0_MAT2/ - RXD PIO1_27/CT32B0_MAT3/ - TXD PIO1_28/CT32B0_CAP0/ - SCLK PIO1_29/SCK0/ - CT32B0_CAP1 PIO1_31 - USB_DM 13 USB_DP 14 XTALIN 4 LPC11U3X Product data sheet Reset Type Description state [ I/O [ ...
Page 15
... NXP Semiconductors Table 3. Pin description Symbol XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption. [2] See Figure 31 for the reset pad configuration ...
Page 16
... NXP Semiconductors 7.4 On-chip ROM The on-chip ROM contains the boot loader and the following Application Programming Interfaces (APIs): • In-System Programming (ISP) and In-Application Programming (IAP) support for flash including IAP erase page command. • IAP support for EEPROM • USB API • ...
Page 17
... NXP Semiconductors LPC11U3x 4 GB reserved private peripheral bus reserved GPIO reserved USB APB peripherals 1 GB reserved 2 kB USB RAM (LPC11U34/421 LPC11U35/401/501 LPC11U36/401/501 LPC11U37/401/501) reserved 2 kB SRAM1 (LPC11U35/501 LPC11U35/501 LPC11U37/501) 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM0 (LPC11U3x) reserved 128 kB on-chip flash (LPC11U37) ...
Page 18
... NXP Semiconductors • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source ...
Page 19
... NXP Semiconductors 7.8.1 Features • GPIO pins can be configured as input or output by software. • All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. • eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • ...
Page 20
... NXP Semiconductors The USART uses a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.10.1 Features • Maximum USART data bit rate of 3.125 Mbit/s. • 16 byte receive and transmit FIFOs. • Register locations conform to 16C550 industry standard. ...
Page 21
... NXP Semiconductors 7.12.1 Features • The I interface supports Fast-mode Plus with bit rates Mbit/s. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • ...
Page 22
... NXP Semiconductors • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • four external outputs corresponding to match registers, with the following capabilities: – ...
Page 23
... NXP Semiconductors 7.17 Clocking and power control 7.17.1 Integrated oscillators The LPC11U3x include three independent oscillators: the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11U3x operates from the internal RC oscillator until software switches to a different clock source ...
Page 24
... NXP Semiconductors IRC oscillator watchdog oscillator IRC oscillator system oscillator SYSPLLCLKSEL (system PLL clock select) system oscillator USBPLLCLKSEL (USB clock select) Fig 7. LPC11U3x clocking generation block diagram 7.17.1.1 Internal RC oscillator The IRC can be used as the clock source for the WDT, and/or as the clock that drives the system PLL and then the CPU ...
Page 25
... NXP Semiconductors 7.17.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC11U3x, use the system oscillator to provide the clock source to USB. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency the maximum CPU operating frequency, by the system PLL ...
Page 26
... NXP Semiconductors consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.17.5.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile ...
Page 27
... NXP Semiconductors Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 7.17.5.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin. The LPC11U3x can wake up from Deep power-down mode via the WAKEUP pin. ...
Page 28
... NXP Semiconductors 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. ...
Page 29
... NXP Semiconductors 7.18 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH) ...
Page 30
... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and DD external rail) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
Page 31
... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current ...
Page 32
... NXP Semiconductors Table 5. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7) I LOW-level input current V ...
Page 33
... NXP Semiconductors Table 5. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter 2 I C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys I LOW-level output OL current I LOW-level output OL current I input leakage current ...
Page 34
... NXP Semiconductors [7] USB_DP and USB_DM pulled LOW externally. [8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [9] IRC disabled; system oscillator enabled; system PLL enabled. [10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode. ...
Page 35
... NXP Semiconductors Table 6. ADC static characteristics − ° ° +85 C unless otherwise specified; ADC frequency 4.5 MHz, V amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
Page 36
... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
Page 37
... NXP Semiconductors 9.1 BOD static characteristics Table amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the LPC11Uxx user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see the LPC11Uxx user manual): • ...
Page 38
... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Typical supply current versus temperature in Active mode ...
Page 39
... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 11. Typical supply current versus temperature in Sleep mode (μA) Fig 12. Typical supply current versus temperature in Deep-sleep mode LPC11U3X Product data sheet ...
Page 40
... NXP Semiconductors (μA) Fig 13. Typical supply current versus temperature in Power-down mode (μA) Fig 14. Typical supply current versus temperature in Deep power-down mode 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers ...
Page 41
... NXP Semiconductors Table 8. Peripheral IRC System oscillator at 12 MHz Watchdog oscillator at 500 kHz/2 BOD Main PLL ADC CLKOUT CT16B0 CT16B1 CT32B0 CT32B1 GPIO IOCONFIG I2C ROM SPI0 SPI1 UART WWDT USB LPC11U3X Product data sheet Power consumption for individual analog and digital blocks ...
Page 42
... NXP Semiconductors 9.4 Electrical pin characteristics V Fig 15. High-drive output: Typical HIGH-level output voltage V (mA) Fig 16. I LPC11U3X Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 Conditions 3 pin PIO0_7. DD output current 0.2 Conditions 3 pins PIO0_4 and PIO0_5. ...
Page 43
... NXP Semiconductors (mA) Fig 17. Typical LOW-level output current I V Fig 18. Typical HIGH-level output voltage V LPC11U3X Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...
Page 44
... NXP Semiconductors (μA) Fig 19. Typical pull-up current I (μA) Fig 20. Typical pull-down current I LPC11U3X Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. DD versus input voltage ° °C −40 °C ...
Page 45
... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash memory Table 9. − amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Table 10. − amb 10 ppm for parts as specified below. ...
Page 46
... NXP Semiconductors Fig 21. External clock timing (with an amplitude of at least V 10.3 Internal oscillators Table 12. − amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply [2] voltages ...
Page 47
... NXP Semiconductors [2] The typical frequency spread over processing and temperature (T [3] See the LPC11Uxx user manual. 10.4 I/O pins Table 14. − amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.5 I C-bus Table 15. Dynamic characteristic: I − ° ° [ +85 C ...
Page 48
... NXP Semiconductors [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t ...
Page 49
... NXP Semiconductors 10.6 SSP interface Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter SPI master (in SPI mode) T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time in SPI mode v(Q) t data output hold time in SPI mode ...
Page 50
... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP master timing in SPI mode LPC11U3X Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 April 2012 ...
Page 51
... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 25. SSP slave timing in SPI mode LPC11U3X Product data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 April 2012 ...
Page 52
... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC11Uxx Fig 26. USB interface on a self-powered device LPC11Uxx Fig 27. USB interface on a bus-powered device 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
Page 53
... NXP Semiconductors Fig 28. Slave mode operation of the on-chip oscillator In slave mode, couple the input clock signal with a capacitor of 100 pF amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected ...
Page 54
... NXP Semiconductors Table 17. Fundamental oscillation frequency F 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 18. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines Follow these guidelines for PCB layout: • Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip. • ...
Page 55
... NXP Semiconductors 11.4 Standard I/O pad configuration Figure 30 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output driver pin configured as digital input data input pin configured as analog input Fig 30 ...
Page 56
... NXP Semiconductors 11.5 Reset pad configuration Fig 31. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC11U3x chip. ...
Page 57
... NXP Semiconductors 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (mm are the original dimensions) (1) (1) Unit max 0.05 0.30 mm nom 0.85 0.2 min 0.00 0.18 Note 1 ...
Page 58
... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 59
... NXP Semiconductors TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm ball A1 index area ball index area Dimensions Unit max 1.10 0.30 0.80 0.35 mm nom 0.95 0.25 0.70 0.30 min 0.85 0.20 0.65 0.25 Outline version IEC SOT1155-2 Fig 34. Package outline TFBGA48 (SOT1155-2) ...
Page 60
... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 61
... NXP Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 62
... NXP Semiconductors 13. Soldering Footprint information for reflow soldering of HVQFN33 package see detail X Hy solder land solder paste occupied area Dimensions 0.5 5.95 5.95 4.25 4.25 11-11-15 Issue date 11-11-20 Fig 37. Reflow soldering for the HVQFN33 (5x5) package LPC11U3X Product data sheet Hx Gx nSPx SLy Gy C SLx ...
Page 63
... NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 38. Reflow soldering for the HVQFN33 (7x7) package LPC11U3X Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5.80 CU LaD = 7 ...
Page 64
... NXP Semiconductors Footprint information for reflow soldering of TFBGA48 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.50 0.225 0.275 0.325 Fig 39. Reflow soldering for the TFBGA48 package LPC11U3X Product data sheet ...
Page 65
... NXP Semiconductors Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 40. Reflow soldering for the LQFP48 package LPC11U3X Product data sheet (8× Generic footprint pattern ...
Page 66
... NXP Semiconductors Footprint information for reflow soldering of LQFP64 package solder land occupied area DIMENSIONS 0.500 0.560 13.300 13.300 10.300 10.300 Fig 41. Reflow soldering for the LQFP64 package LPC11U3X Product data sheet (0.125) D2 (8× ...
Page 67
... NXP Semiconductors 14. Revision history Table 19. Revision history Document ID Release date LPC11U3X v.1 20120420 LPC11U3X Product data sheet Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 April 2012 LPC11U3x 32-bit ARM Cortex-M0 microcontroller Change notice ...
Page 68
... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 69
... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 70
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 15 7.1 On-chip flash programming memory . . . . . . . 15 7.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5 Memory map 7.6 Nested Vectored Interrupt Controller (NVIC ...