LPC11U35FHI33/501, NXP Semiconductors, LPC11U35FHI33/501, Datasheet - Page 29

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LPC11U35FHI33/501,

Manufacturer Part Number
LPC11U35FHI33/501,
Description
ARM Microcontrollers - MCU 32-bit ARM Cortex-M0 64KB Flash 12KB SRAM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC11U35FHI33/501,

Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC11U3x
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
64 KB
Data Ram Size
12 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
HVQFN-32
Mounting Style
SMD/SMT
Factory Pack Quantity
490
NXP Semiconductors
LPC11U3X
Product data sheet
7.18 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11U3x is in reset.
To perform boundary scan testing, follow these steps:
Remark: The JTAG interface cannot be used for debug purposes.
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 μs.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 April 2012
32-bit ARM Cortex-M0 microcontroller
LPC11U3x
© NXP B.V. 2012. All rights reserved.
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