LPC11U35FHI33/501, NXP Semiconductors, LPC11U35FHI33/501, Datasheet - Page 48

• Manufacturer Part Number: LPC11U35FHI33/501,
• Description: ARM Microcontrollers - MCU 32-bit ARM Cortex-M0 64KB Flash 12KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11U35FHI33/501,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11U3x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-32
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 490

NXP Semiconductors
[7]
[8]
[10] A Fast-mode I
LPC11U3X
Product data sheet
[9]
Fig 23. I
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
The maximum t
t
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
Standard-mode I
VD;ACK
SDA
SCL
by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t
2
C-bus pins clock timing
70 %
30 %
S
2
t
C-bus device can be used in a Standard-mode I
f
HD;DAT
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t
f
could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t
70 %
30 %
1 / f
SCL
t
HD;DAT
70 %
30 %
70 %
30 %
All information provided in this document is subject to legal disclaimers.
t
SU;DAT
Rev. 1 — 20 April 2012
70 %
30 %
2
C-bus system but the requirement t
t
LOW
r(max)
t
HIGH
+ t
32-bit ARM Cortex-M0 microcontroller
70 %
30 %
SU;DAT
t
VD;DAT
= 1000 + 250 = 1250 ns (according to the
SU;DAT
= 250 ns must then be met.
LPC11U3x
© NXP B.V. 2012. All rights reserved.
002aaf425
LOW
VD;DAT
48 of 70
) of the
or