LPC11U35FHI33/501, NXP Semiconductors, LPC11U35FHI33/501, Datasheet - Page 27

• Manufacturer Part Number: LPC11U35FHI33/501,
• Description: ARM Microcontrollers - MCU 32-bit ARM Cortex-M0 64KB Flash 12KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11U35FHI33/501,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11U3x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-32
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 490

NXP Semiconductors
LPC11U3X
Product data sheet
7.17.5.5 Deep power-down mode
7.17.6.1 Reset
7.17.6.2 Brownout detection
7.17.6.3 Code security (Code Read Protection - CRP)
7.17.6 System control
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pin. The LPC11U3x can wake up from Deep power-down mode via the WAKEUP pin.
The LPC11U3x can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU block. Locking out Deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in
Deep power-down mode.
Reset has four sources on the LPC11U3x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
The LPC11U3x includes four levels for monitoring the voltage on the V
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a
dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details, see the LPC11Uxx user manual.
There are three levels of Code Read Protection:
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 April 2012
32-bit ARM Cortex-M0 microcontroller
LPC11U3x
DD
© NXP B.V. 2012. All rights reserved.
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