iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet
iCE65L08F-LCB196C
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iCE65L08F-LCB196C Summary of contents
Page 1
... RAM4K Memory Blocks RAM4K RAM bits Configuration bits (maximum) Typical Current at 0 kHz, 1.0 V Maximum Programmable I/O Pins Maximum Differential Input Pairs © 2007-2012 by Lattice Semiconductor Corporation. All rights reserved. www.latticesemi.com Figure 1: iCE65 Family Architectural Features 12 µ kHz (Typical) I/O Bank 0 Programmable Interconnect ...
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... Ultra Low-Power mobileFPGA Overview The Lattice Semiconductor iCE65 programmable logic family is specifically designed to deliver the lowest static and dynamic power consumption of any comparable CPLD or FPGA device. iCE65 devices are designed for cost- sensitive, high-volume applications and provide on-chip, nonvolatile configuration memory (NVCM) to customize for a specific application ...
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... The common footprint improves manufacturing flexibility. Different models of the same product can share a common circuit board. Feature-rich versions of the end application mount a larger iCE65 device on the circuit board. Low-end versions mount a smaller iCE65 device. Lattice Semiconductor Corporation www.latticesemi.com ™ are available for die stacking and highly space-conscious applications. All ...
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... QN = quad flat no-lead package iCE65 Ordering Codes NVCM Programmed Device Temperature Range = Commercial 0° to 70° Celsius Industrial –40° to 85° Celsius Package Leads Package Style NVCM Program Code Revision Customer Program Code Lattice Semiconductor Corporation www.latticesemi.com ...
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... Programmable Logic Block (PLB) Generally, a logic design for an iCE65 component is created using a high-level hardware description language such as Verilog or VHDL. The Lattice Semiconductor development software then synthesizes the high-level description into equivalent functions built using the programmable logic resources within each iCE65 device. Both sequential and combinational functions are constructed from an array of Programmable Logic Blocks (PLBs) ...
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... The asterisk indicates that this is the default state if the control signal is Carry Logic function, Figure 4. Table 3 describes the Inputs Output EN SR CLK ↑ ↑ ↑ 1 Table 3. The asterisk indicates that Lattice Semiconductor Corporation www.latticesemi.com ...
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... Carry Logic. The example is a 2-bit adder, which can be expanded into an adder of arbitrary size. The LUT4 function within a Logic Cell is programmed to calculate the sum of the two input values and the carry input, A[i] + B[i] + CARRY_IN[i-1] = SUM[i]. Lattice Semiconductor Corporation www.latticesemi.com Table 4 ...
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... Carry Logic Structure within a Logic Cell and between PLBs (2.42, 30-MAR-2012) 8 ™ Family Adjacent PLB To upper adjacent Logic Cell Carry Logic I0 I1 LUT4 I2 I3 From lower adjacent Logic Cell Carry Logic initialization into Programmable Logic Block (PLB Adjacent PLB = Statically defined by configuration program Lattice Semiconductor Corporation www.latticesemi.com ...
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... The Carry Logic does not specifically have a subtract mode. To implement a subtract function or decrement function, logically invert either the input and invert the initial carry input. This performs a 2s complement subtract operation. GND GND A[1] B[1] A[0] B[0] CARRY_IN Lattice Semiconductor Corporation www.latticesemi.com Figure 6: Two-bit Adder Example LUT4 Carry Logic ...
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... GBIN pins optionally connect directly to an associated GBUF global buffer Programmable Input/Output Table 50 2.5V 1.8V 1.5V Yes Yes Outputs only Yes Yes Outputs only Yes Yes Outputs only Yes Yes iCE65L01: Outputs only iCE65L04/08: Yes Yes Yes No Lattice Semiconductor Corporation www.latticesemi.com Table 5. and Table ...
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... Supply I/O Standard Voltage LVCMOS33 3.3V LVCMOS25 2.5V LVCMOS18 1.8V LVCMOS15 1.5V SSTL2_II 2.5V SSTL2_I SSTL18_II 1.8V SSTL18_I MDDR 1.8V LVDS 2.5V Lattice Semiconductor Corporation www.latticesemi.com Supply Voltage Drive Current (mA) 3.3V 3.3V 2.5V 1.8V 1.5V Table 7 lists the various I/O standards supported by I/O Bank 3. for electrical characteristics. VREF Pin (CB284 or DiePlus) Required Yes Yes No No ...
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... The DPxxB receives the true version of the signal while the DPxxA receives 1.8V 1.5V Any SB_LVCMOS18 Any SB_LVCMOS15 SB_SSTL18_FULL SB_SSTL18_HALF SB_MDDR10 SB_MDDR8 SB_MDDR4 SB_MDDR2 SB_LVDS_INPUT Table 8. For the LVCMOS and 8. Differential outputs are available in all four “Differential Inputs” on page 100. Figure 8. Lattice Semiconductor Corporation www.latticesemi.com ...
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... For electrical characteristics, see The PIO pins that make up a differential output pair are indicated with a blue bounding box in the in the tables in “Die Cross Reference” starting on page 84. Lattice Semiconductor Corporation www.latticesemi.com Differential Inputs in iCE65L04 and iC65L08 I/O Bank 3 Impedance-matched signal traces VCCIO_3 = 1.8V or 2.5V 50Ω ...
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... PAD Input Pull- Input Value to Up Enabled? Pin Value Interconnect X PAD PAD Value No Z (Undefined) Yes Z X PAD PAD Value No Z (Undefined) Yes Last Captured PAD Value Lattice Semiconductor Corporation www.latticesemi.com Table ...
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... After iCE65 configuration is complete, the input pull-up resistor is optional, defined by a configuration bit. The pull-up resistor is also useful to tie off unused PIO pins. The Lattice iCEcube development software defines all unused PIO pins in I/O Banks 0, 1 and 2 as inputs with the pull-up resistor turned on. The pull-up resistor value ...
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... Family Statically defined by configuration program “Die Cross Reference” starting on page 84. Figure 11. The combinational logic paths Figure 11. By default, the tables in “Die PIO Pair Output Enabled PAD Output Enabled PAD Lattice Semiconductor Corporation www.latticesemi.com ...
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... The DDR flip-flops provide several design advantages. Internally within the iCE65 device, the clock frequency is half the effective external data rate. The lower clock frequency eases internal timing, doubling the clock period, and slashes the clock-related power in half. Lattice Semiconductor Corporation www.latticesemi.com Figure 12: DDR Output Flip-Flop ...
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... Clock Yes Yes Yes Yes Yes Yes Yes Yes Figure 14. There are eight high- GBIN2 Global Buffer GBUF2 GBUF3 Global Buffer GBIN3 Clock Enable Reset Yes No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Lattice Semiconductor Corporation www.latticesemi.com ...
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... GBIN input appear in Table 14: Global Buffer I/O Input (GBIN) Bank GBIN0 0 GBIN1 GBIN2 1 GBIN3 GBIN4 2 GBIN5 GBIN6 3 GBIN7 Lattice Semiconductor Corporation www.latticesemi.com Output Input Clock Yes PLB LUT) Yes Yes Yes Yes Yes Yes Yes Output Input Clock Yes PLB LUT) Yes ...
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... N/A 12 N/A VCCIO Output Enabled Pull-up not in I/O Bank 3 Pull-up Enable PAD Latch inhibits switching for lowest power GBIN pins optionally connect directly to an associated GBUF global buffer GBUF7 ‘L04 ‘L08 CB196 CB196 Lattice Semiconductor Corporation www.latticesemi.com Figure 16. CB284 L5 L3 ...
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... Random-access memory (RAM) Single-port RAM with a common address, enable, and clock control lines Two-port RAM with separate read and write control lines, address inputs, and enable Lattice Semiconductor Corporation www.latticesemi.com Figure 11. Figure Figure 17: RAM4K Memory Block Write Port ...
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... Write Clock input. Default rising-edge, but with falling-edge option. Read Data output. Read Address input. Selects one of 256 possible RAM locations. Read Enable input. Read Clock Enable input. Read Clock input. Default rising-edge, but with falling-edge option. Figure 18. Figure Description Table 18 describes various write Lattice Semiconductor Corporation www.latticesemi.com 17. ...
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... Read Operations Figure 19 shows the logic involved in reading a location from RAM. RAM4K block. By default, all RAM4K read operations are synchronized to the rising edge of RCLK although the clock is invertible as shown in Lattice Semiconductor Corporation www.latticesemi.com Figure 18: RAM4K Bit Write Logic MASK[BIT] WE WCLKE ...
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... Table 19: RAM4K Read Operations RADDR[7:0] RE Read Address Enable RADDR 1 Option” for more information RDATA[15:0] EN RCLKE RCLK Clock Enabe Clock RDATA[15: Undefined Change Change change RAM[RADDR] ↑ 1 “Cold Boot Configuration Lattice Semiconductor Corporation www.latticesemi.com Option” ...
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... Table 20, iCE65 components are configured for a specific application by loading a binary configuration bitstream image, generated by the Lattice development system. For high-volume applications, the bitstream image is usually permanently programmed in the on-chip NVCM, However, the bitstream image can also be stored external in a standard, low-cost commodity SPI serial Flash PROM. The iCE65 component can ...
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... Configuration? No Configure from SPI Flash PROM CDONE = 1 After configuration ends, pulse the CRESET_B pin No Low for 250 ns or longer to CRESET_B = Low? restart configuration process or cycle the power Yes Configure as SPI Configure from Periphal NVCM Configure from NVCM Lattice Semiconductor Corporation www.latticesemi.com ...
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... The configuration controller begins configuring the iCE65 device, clocked by the oscillator continues controlling configuration unless the iCE65 device is configured using the Configuration Interface. Lattice Semiconductor Corporation www.latticesemi.com iCE65 Configuration Image Size (Kbits) MINIMUM Logic Only ...
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... High and CDONE. Table 23 lists the ball/pin (Cold Boot). The CRESET_B pin is a pure input CB132 CB196 L10 L10 M10 M10 and when configuring from SPI Peripheral Configuration on page Lattice Semiconductor Corporation www.latticesemi.com CB284 R14 T14 Interface, the 105 for the ...
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... All iCE65 devices, including those with NVCM, can be configured from an external, commodity SPI serial Flash PROM, as shown in Figure 23. The SPI configuration interface is essentially its own independent I/O bank, powered by the VCC_SPI supply input. Presently, most commercially-available SPI serial Flash PROMs require a 3.3V supply. Lattice Semiconductor Corporation www.latticesemi.com Figure 22: iCE65 Internal Reset Circuitry Internal Voltage Thresholds ...
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... The iCE65 mobileFPGA SPI Flash configuration interface supports a variety of SPI Flash memory vendors and product families. However, Lattice Semiconductor does not specifically test, qualify, or otherwise endorse any specific SPI Flash vendor or product family. The iCE65 SPI interface supports SPI PROMs that they meet the following requirements. ...
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... CRESET_B input Low until the PROM is ready, then releasing CRESET_B, either under program control or using an external power-on reset circuit. The Lattice iCEman65 development board and associated programming software uses an ST Micro/Numonyx M25Pxx SPI serial Flash PROM. SPI PROM Size Requirements Table 27 lists the minimum SPI PROM size required to configure an iCE65 device ...
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... Fast Read data Don’t Care Dummy Byte Data Byte 0 SPI_SCK clock output. The iCE65 SPI_SCK clock signal. The To conserve power, the iCE65 device then 0xB9 Deep Power-down Lattice Semiconductor Corporation www.latticesemi.com SPI_SS_B ...
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... If the selected bitstream is in NVCM, then the address points to the internal NVCM. Using the new start address, the FPGA restarts reading configuration memory from the new location. Lattice Semiconductor Corporation www.latticesemi.com ColdBoot and WarmBoot Configuration after reset Jump based ...
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... PIO2/CBSEL1 H5 When creating the initial configuration image, the Lattice development software loads the start address for up to four configuration images in the bitstream. The value on the CBSEL[1:0] pins tell the configuration controller to read a specific start address, then to load the configuration image stored at the selected address. The multiple bitstreams are stored either in the SPI Flash or in the internal NVCM ...
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... CRESET_B pin and allows it to float High via the 10 kΩ pull-up resistor to VCCIO_2 or drives CRESET_B High. The iCE65 FPGA enters SPI peripheral mode when the CRESET_B pin returns High while the SPI_SS_B pin is Low. Lattice Semiconductor Corporation www.latticesemi.com iCE65 SPI Peripheral Configuration Interface ...
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... Family iCE65 captures SPI_SI data on SPI_SCK rising edge. Configuration image always starts with 0x7EAA997E synchronization word. Entire Configuration Images Send most-significant bit of each byte first Lattice Semiconductor Corporation µs, (see Table 60) CR_SCK 49 SPI_SCK Cycles Rising edge to rising edge Don’ ...
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... SPI Peripheral interface, described in Table 30. Table 30: Supply Voltage AP_VCCIO VCC_SPI VCCIO_2 Lattice Semiconductor Corporation www.latticesemi.com SPI Peripheral Configuration Process SPI Peripheral Configuration Drive CRESET_B = 0 Drive SPI_SS_B = 0, SPI_SCK = 1 Wait a minimum of 200 ns Release CRESET_B or drive CRESET_B = 1 Wait a minimum of iC65L01: 800 µ ...
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... AP_VCCIO is also recommended. The AP must control CRESET_B with an open-drain output, which requires a 10 kΩ pull-up resistor to VCCIO_2. The 10 kΩ pull-up resistor to AP_VCCIO is required. Description CB196 CB284 M12 T16 P14 V18 L12 R16 N14 U18 M14 T18 Lattice Semiconductor Corporation www.latticesemi.com ...
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... Similarly, smaller iCE65 devices may have unconnected balls in some packages. Devices sharing a common package have similar footprints. Table 35: Package iCE65L01 CB81 QN84 VQ100 CB132 CB196 CB284 Lattice Semiconductor Corporation www.latticesemi.com Table 35 for device-specific I/O counts by package. Table 34: User I/O by Package, by I/O Bank CB81 QN84 VQ100 81 84 ...
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... Low). An output when in SPI Flash configuration mode. A full-featured PIO pin after configuration. JTAG Test Data Input. If using the JTAG interface, use a 10kΩ pull-up resistor to VCCIO_1. Tie off to GND when unused. Description Figure 20. An Lattice Semiconductor Corporation www.latticesemi.com ...
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... Package Footprint Diagram Conventions Figure 31 illustrates the naming conventions used in the following footprint diagrams. Each PIO pin is associated with an I/O Bank. PIO pins in I/O Bank 3 that support differential inputs are also numbered by differential input pair. Figure 31: Lattice Semiconductor Corporation www.latticesemi.com Pull-up I/O during Bank Config JTAG Test Mode Select. If using the JTAG interface, use a 10kΩ ...
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... SEL1 SPI_SO GBIN4 PIOS/ PIO2 VCC VCCIO_2 CRESET_B /PIO2 SPI_SI I/O Bank GND A VPP_ B 2V5 PIO1 PIO1 C PIO1 D VCCIO_1 PIO1 PIO1 E GBIN3 PIO1 F /PIO1 PIO1 PIO1 G SPI_ PIOS/ H VCC SPI_SS_B PIOS/ GND J SPI_SCK 8 9 Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO1 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 CDONE CRESET_B PIO2 PIO2 PIO2/CBSEL0 PIO2 GBIN5/PIO2 PIO2/CBSEL1 PIO2 GBIN4/PIO2 VCCIO_2 Lattice Semiconductor Corporation www.latticesemi.com iCE65 CB81 Chip-scale BGA Pinout Table Ball Number Pin Type A2 PIO A3 PIO A4 GBIN A7 PIO A8 PIO B4 PIO B5 PIO B6 ...
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... GND A9 GND J9 GND J1 GND E4 GND E5 GND F4 GND F5 GND A5 VCC J5 VCC B9 VPP Bank SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND VCC VCC VPP Lattice Semiconductor Corporation www.latticesemi.com ...
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... Number of Signal Balls Body Size Ball Pitch Ball Diameter Edge Ball Center to Center Package Height Stand Off Top Marking Format Line Content Lattice Semiconductor Corporation www.latticesemi.com CB81 Package Mechanical Drawing Bottom View b Symbol Min. Nominal ...
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... A34 PIO1 PIO1 B26 A33 PIO1 VCCIO_1 B25 A32 PIO1 PIO1 B24 A31 PIO1 PIO1 B23 A30 GND GBIN2/PIO1 B22 A29 GBIN3/PIO1 PIO1 B21 A28 VCC PIO1 B20 A27 PIO1 PIO1 B19 A26 PIO1 A25 PIO1 SPI Bank Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 Lattice Semiconductor Corporation www.latticesemi.com Table 38: iCE65 QN84 Chip-scale BGA Pinout Table Ball Number B32 A43 A38 A39 A40 A41 A44 A45 A46 A47 A48 B29 ...
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... A15 VCC A28 VCC B28 VCC A36 VPP A37 VPP Bank SPI SPI SPI SPI SPI GND GND GND GND VCC VCC VCC VCC VPP VPP Lattice Semiconductor Corporation www.latticesemi.com ...
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... CCCCCC Side View Top Marking Format Line Content 1 Logo iCE65L01F 2 -T QN84C 3 ENG 4 NXXXXXXX 5 YYWW 6 © CCCCCC Lattice Semiconductor Corporation www.latticesemi.com Figure 35: QN84 Package Mechanical Drawing A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 0.50 Notes: 1. All dimensions are in millimeters ...
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... Table 39) (L01 only, see Table 40) VPP_2V5 75 PIO1 74 PIO1 73 PIO1 72 PIO1 71 R GND 70 PIO1 69 PIO1 68 VCCIO_1 67 PIO1 66 PIO1 65 PIO1 64 PIO1 63 GBIN2/ PIO1 62 GBIN3/ VCC 61 PIO1 60 PIO1 59 VCCIO_1 58 PIO1 57 PIO1 56 GND 55 PIO1 54 PIO1 53 PIO1 52 SPI Bank PIO1 51 Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 VCCIO_1 VCCIO_1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 Lattice Semiconductor Corporation www.latticesemi.com Table 39: iCE65 VQ100 Pinout Table Pin Number ...
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... GND 98 GND 11 VCC 35 VCC Bank SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND GND GND VCC VCC Lattice Semiconductor Corporation www.latticesemi.com ...
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... Y X Edge Pin Center to Center Y Lead Pitch Lead Width Total Package Height Stand Off Body Thickness Lead Length Lead Thickness Coplanarity Lattice Semiconductor Corporation www.latticesemi.com Pin Number Top View Mark pin 1 dot 100 1 Pin 1 indicator iCE65L01F-T ENG VQ100C NXXXXXXX YYWW © ...
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... Logo Logo iCE65L01F Part number 2 -T Power/Speed ENG Engineering 3 VQ100C Package type and NXXXXXXX Lot number 4 ZZZZZZZZ NVCM Program. code 5 YYWW Date Code mm 6 © CCCCCC Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 38 32 Lattice Semiconductor Corporation www.latticesemi.com ...
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... CB121 chip-scale BGA package. Pins are generally arranged by I/O bank, then by ball function. Table 40: Ball Function GBIN0/PIO0 GBIN1/PIO0 PIO0 PIO0 PIO0 Lattice Semiconductor Corporation www.latticesemi.com iCE65L01 CB121 Chip-Scale BGA Footprint (Top View) I/O Bank ...
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... VCCIO J7 CONFIG K7 CONFIG L8 GBIN L9 GBIN H4 PIO H5 PIO H11 PIO J4 PIO J5 PIO Bank Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO3 PIO3 PIO3 PIO3 PIO3 PIO3 VCCIO_3 VCCIO_3 PIOS/SPI_SO PIOS/SPI_SI PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC GND GND GND GND GND GND GND GND Lattice Semiconductor Corporation www.latticesemi.com Ball Number Pin Type J11 PIO K3 PIO K4 PIO K11 PIO L2 PIO L3 PIO L4 PIO L5 PIO L10 PIO ...
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... Ball Function GND GND VCC VCC VCC VCC VPP_2V5 VPP_FAST (2.42, 30-MAR-2012) 58 ™ Family Ball Number Pin Type K2 GND K10 GND B6 VCC F1 VCC F11 VCC K6 VCC C10 VPP A9 VPP Bank GND GND VCC VCC VCC VCC VPP VPP Lattice Semiconductor Corporation www.latticesemi.com ...
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... Side View Description Number of Ball Columns Number of Ball Rows Number of Signal Balls Body Size Ball Diameter Edge Ball Center to Center Package Height Top Marking Format Li ne Content Lattice Semiconductor Corporation www.latticesemi.com Figure 40: CB121 Package Mechanical Drawing Top View Symbol Min ...
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... PIO1 GBIN2/ PIO1 PIO1 G PIO1 PIO1 PIO1 H VCCIO_1 PIO1 PIO1 GND J PIO1 PIO1 PIO1 K SPI_ TCK PIO1 L CRESET_B VCC PIOS/ TDI M CDONE TRST_B SPI_SO TDO N SPI Bank PIOS/ PIOS/ PIOS/ TMS P CBSEL1 SPI_SI SPI_SCK SPI_SS_B Lattice Semiconductor Corporation www.latticesemi.com ...
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... DP08A PIO3/ GND L DP09A PIO3/ PIO2 M DP09B PIO3/ N DP10A PIO3/ PIO2 PIO2 PIO2 PIO2 P DP10B Lattice Semiconductor Corporation www.latticesemi.com iCE65L04 CB132 Chip-Scale BGA Footprint (Top View) I/O Bank GBIN0/ GBIN1/ GND VCCIO_0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 ...
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... PIO1 GBIN2/ PIO1 PIO1 G PIO1 PIO1 PIO1 H VCCIO_1 PIO1 PIO1 GND J PIO1 PIO1 PIO1 K SPI_ TCK PIO1 L CRESET_B VCC PIOS/ TDI M CDONE TRST_B SPI_SO TDO N SPI Bank PIOS/ PIOS/ PIOS/ TMS P CBSEL1 SPI_SI SPI_SCK SPI_SS_B Lattice Semiconductor Corporation www.latticesemi.com ...
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... VCCIO_0 VCCIO_0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 Lattice Semiconductor Corporation www.latticesemi.com iCE65 CB132 Chip-scale BGA Pinout Table Ball Number Pin Type iCE65L01: A7 iCE65L04/L08: A6 iCE65L01: A6 iCE65L04/08 iCE65L01: (NC) iCE65L04: PIO0 A4 A5 A10 ...
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... PIO B1 DPIO C1 DPIO C3 DPIO D3 DPIO D4 DPIO E4 DPIO D1 DPIO E1 DPIO F4 DPIO F3 DPIO H1 GBIN Bank Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIOS/SPI_SCK PIOS/SPI_SS_B SPI_VCC GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VPP_2V5 VPP_FAST Lattice Semiconductor Corporation www.latticesemi.com Ball Number Pin Type G1 GBIN G3 DPIO G4 DPIO H3 DPIO H4 DPIO J3 DPIO J1 DPIO K3 DPIO K4 DPIO L1 DPIO ...
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... Line Content Description Columns 1 Logo Logo Rows iCE65L04F Part number Balls 2 -T Power/Speed CB132C Package type 3 ENG Engineering 4 NXXXXXXX Lot Number 5 YYWW Date Code mm 6 © CCCCCC Country Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 42 34 Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO3/ PIO2 PIO2 M DP15A DP15B PIO3/ PIO3/ PIO2 PIO2 PIO2 PIO2 N DP17A DP17B PIO2 PIO2 PIO2 PIO2 Lattice Semiconductor Corporation www.latticesemi.com Figure Table 42 iCE65L04 CB196 Chip-Scale BGA Footprint (Top View) I/O Bank GBIN0/ PIO0 PIO0 GND VCCIO_0 ...
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... CRESET_B VCC PIOS/ TDI PIO1 M CDONE TRST_B SPI_SO PIO2 PIO2 PIO2 TDO N VCCIO_2 PIO2/ PIOS/ PIOS/ PIOS/ TMS P CBSEL1 SPI_SI SPI_SCK SPI_SS_B SPI Bank almost Table 43. Pin Type Bank GBIN 0 GBIN 0 PIO 0 PIO 0 PIO 0 PIO 0 Lattice Semiconductor Corporation www.latticesemi.com ...
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... VCCIO_0 VCCIO_0 GBIN2/PIO1 GBIN3/PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 PIO1 Lattice Semiconductor Corporation www.latticesemi.com Ball Number Pin Type A5 PIO A6 PIO A10 PIO A11 PIO A12 PIO B2 PIO B3 PIO B4 PIO B5 PIO ...
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... PIO M6 PIO iCE65L04: PIO M7 iCE65L08 PIO M9 PIO N3 PIO N4 PIO N5 PIO N6 PIO Bank Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO3/DP05A () PIO3/DP05B () PIO3/DP06A PIO3/DP06B PIO3/DP07A () GBIN7/PIO3/DP07B () GBIN6/PIO3/DP08A PIO3/DP08B PIO3/DP09A PIO3/DP09B PIO3/DP10A PIO3/DP10B PIO3/DP11A () PIO3/DP11B () PIO3/DP12A PIO3/DP12B Lattice Semiconductor Corporation www.latticesemi.com Ball Number Pin Type iCE65L04: PIO N8 iCE65L08 PIO N11 PIO N12 PIO N13 PIO ...
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... SPI SPI SPI SPI SPI GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VPP VPP Lattice Semiconductor Corporation www.latticesemi.com ...
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... F3 PIO3/DP05A F4 PIO3/DP05B G1 GBIN7/PIO3/DP07B G2 PIO3/DP07A H3 PIO3/DP11B H4 PIO3/DP11A K3 PIO3/DP16A K4 PIO3/DP16B L7 GBIN4/PIO2 GBIN5/PIO2 Lattice Semiconductor Corporation www.latticesemi.com iCE65L04 iCE65L08 PIO3/DP03B PIO3/DP03A PIO3/DP05B PIO3/DP05A PIO3/DP11A PIO3/DP11B GBIN7/PIO3/DP07B PIO3/DP07A PIO3/DP16B PIO3/DP16A PIO2 PIO2 GBIN4/PIO2 PIO2 GBIN5/PIO2 PIO2 Functional Difference Differential inputs swapped, single-ended I/Os not affected ...
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... Line Content Description Units 1 Logo Logo Columns iCE65L04F Part number Rows 2 -T Power/Speed Balls CB196I Package type 3 ENG Engineering 4 NXXXXXXX Lot Number 5 YYWW Date Code 6 © CCCCCC Country mm Thermal Resistance Junction-to-Ambient θ (⁰C/W) 0 LFM 200 LFM 42 34 Lattice Semiconductor Corporation www.latticesemi.com ...
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... Top Marking Format Line Content Description Units 1 Logo Logo Columns iCE65L08F Part number Rows 2 -T Power/Speed Balls CB196C Package type 3 ENG Engineering 4 NXXXXXXX Lot Number 5 YYWW Date Code 6 © CCCCCC Country mm Thermal Resistance Junction-to-Ambient θ ...
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... PIO1 PIO1 TRST_B SPI_SO TDO PIO1 PIO1 SPI Bank PIOS/ PIOS/ PIOS/ TMS PIO1 PIO1 SPI_SI SPI_SCK SPI_SS_B PIO1 PIO1 GND PIO2 PIO2 PIO2 PIO2 PIO1 PIO1 Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 PIO0 Lattice Semiconductor Corporation www.latticesemi.com ) are unconnected balls (N.C.) for the iCE65L04 in the Pin Type by Device iCE65L04 iCE65L08 iCE65L04 E10 GBIN E11 GBIN A1 N.C. A2 N.C. A3 N.C. ...
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... PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 PIO 1 Lattice Semiconductor Corporation www.latticesemi.com CB132 Ball Equivalent A11 A12 C10 C11 C12 D10 D11 — — G14 F14 — — ...
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... TRST_B VCCIO_1 VCCIO_1 VCCIO_1 VCCIO_1 CDONE CRESET_B GBIN4/PIO2 GBIN5/PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 PIO2 Lattice Semiconductor Corporation www.latticesemi.com Pin Type by Device iCE65L04 iCE65L08 iCE65L04 L15 PIO L16 PIO L22 N.C. M15 PIO M16 PIO M20 PIO M22 N ...
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... PIO 2 PIO 2 PIO 2 PIO 2 VCCIO 2 VCCIO 2 VCCIO 2 DPIO 3 DPIO 3 DPIO 3 DPIO 3 DPIO 3 DPIO 3 Lattice Semiconductor Corporation www.latticesemi.com CB132 Ball Equivalent — — — — — — — — — — — — — — — — — — ...
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... PIO3/DP14B () GBIN6/PIO3/DP15A PIO3/DP15B PIO3/DP16A PIO3/DP16B PIO3/DP17A PIO3/DP17B PIO3/DP18A PIO3/DP18B PIO3/DP19A PIO3/DP19B PIO3/DP20A PIO3/DP20B PIO3/DP21A PIO3/DP21B PIO3/DP22A PIO3/DP22B PIO3/DP23A PIO3/DP23B PIO3/DP24A PIO3/DP24B VCCIO_3 VCCIO_3 Lattice Semiconductor Corporation www.latticesemi.com Pin Type by Device iCE65L04 iCE65L08 iCE65L04 H5 DPIO J5 DPIO K8 DPIO K7 DPIO E3 DPIO F3 DPIO G3 DPIO H3 DPIO B1 N ...
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... VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VPP VPP VPP VPP Lattice Semiconductor Corporation www.latticesemi.com CB132 Ball Equivalent E3 — — — M11 P11 P12 P13 L11 — A9 — ...
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... D1 10.50 — — A 1.00 — A1 0.16 0.26 Bottom View Top Marking Format Line Content Description 1 Logo Logo iCE65L08F Part number 2 -T Power/Speed ENG Engineering 3 CB284C Package type and NXXXXXXX Lot number 4 YYWW Date Code 5 N/A Blank 6 © CCCCCC Country Thermal Resistance Junction-to-Ambient θ ...
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... Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO3_30/DP15A PIO3_31/DP15B VCC PIO3_32/DP16A PIO3_33/DP16B VCCIO_3 VCCIO_3 GND GND PIO3_34/DP17A PIO3_35/DP17B PIO3_36/DP18A PIO3_37/DP18B PIO3_38/DP19A PIO3_39/DP19B PIO2_00 PIO2_01 PIO2_02 GND PIO2_03 PIO2_04 PIO2_05 PIO2_06 PIO2_07 Lattice Semiconductor Corporation www.latticesemi.com DiePlus VQ100 CB132 CB196 CB284 12 — N10 N/A N/A N/A M1 — — ...
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... Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO1_08 PIO1_09 PIO1_10 VCC VCC PIO1_11 PIO1_12 PIO1_13 PIO1_14 PIO1_15 PIO1_16 PIO1_17 GND GND PIO1_18 GBIN3/PIO1_19 GBIN2/PIO1_20 PIO1_21 VCCIO_1 VCCIO_1 PIO1_22 PIO1_23 Lattice Semiconductor Corporation www.latticesemi.com DiePlus VQ100 CB132 CB196 CB284 44 L10 L10 R14 45 M11 M11 T15 46 P11 P11 V15 47 — P6 ...
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... Lattice Semiconductor Corporation www.latticesemi.com ...
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... GND PIO0_32 PIO0_33 PIO0_34 PIO0_35 PIO0_36 VCCIO_0 VCCIO_0 PIO0_37 PIO0_38 PIO0_39 PIO0_40 PIO0_41 PIO0_42 GND PIO0_43 PIO0_44 PIO0_45 PIO0_46 PIO0_47 Lattice Semiconductor Corporation www.latticesemi.com DiePlus VQ100 CB132 CB196 CB284 — — — C19 — — C9 C18 — — B9 C17 — — ...
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... Lattice Semiconductor Corporation www.latticesemi.com ...
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... GND PIO3_32/DP16A PIO3_33/DP16B VCCIO_3 VCCIO_3 GND GND PIO3_34/DP17A PIO3_35/DP17B PIO3_36/DP18A PIO3_37/DP18B PIO3_38/DP19A PIO3_39/DP19B PIO3_40/DP20A PIO3_41/DP20B VCC VCC PIO3_42/DP21A PIO3_43/DP21B VCCIO_3 VCCIO_3 GND GND Lattice Semiconductor Corporation www.latticesemi.com Available Packages CB196 CB284 — H8 — N10 — — N/A M1 N/A — — ...
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... Lattice Semiconductor Corporation www.latticesemi.com ...
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... VCCIO_2 PIO2_47 GND GND PIO2_48 PIO2_49 PIO2_50 PIO2_51/CBSEL0 PIO2_52/CBSEL1 CDONE CRESET_B PIOS_00/SPI_SO PIOS_01/SPI_SI GND GND PIOS_02/SPI_SCK PIOS_03/SPI_SS_B VCC VCC SPI_VCC SPI_VCC Lattice Semiconductor Corporation www.latticesemi.com Available Packages CB196 CB284 — Y13 M7 V11 N8 V12 J8 Y12 — — P8 Y14 — AB15 M8 V13 — ...
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... Lattice Semiconductor Corporation www.latticesemi.com ...
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... GND GND PIO1_51 PIO1_52 PIO1_53 PIO1_54 VPP_2V5 VPP_FAST VCC VCC PIO0_00 PIO0_01 PIO0_02 PIO0_03 PIO0_04 VCCIO_0 PIO0_05 PIO0_06 PIO0_07 Lattice Semiconductor Corporation www.latticesemi.com Available Packages CB196 CB284 — K20 G14 F22 — G22 F11 E22 F12 L16 G13 D22 G8 L12 — ...
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... Lattice Semiconductor Corporation www.latticesemi.com ...
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... PIO0_42 PIO0_43 PIO0_44 PIO0_45 PIO0_46 PIO0_47 PIO0_48 VCCIO_0 VCCIO_0 PIO0_49 PIO0_50 PIO0_51 PIO0_52 PIO0_53 PIO0_54 GND GND PIO0_55 PIO0_56 PIO0_57 PIO0_58 PIO0_59 Lattice Semiconductor Corporation www.latticesemi.com Available Packages CB196 CB284 — A4 — A2 — C7 — K10 — — ...
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... Minimum Nominal Maximum 0.95 1.00 1.05 1.14 1.20 1.26 1.30 — 3.47 2.30 — 3.47 2.30 — 3.00 Leave unconnected in application 1.71 — 3.47 3.14 3.30 3.47 Nominal 2.5< Nominal Nominal -5% <3.3 +5% 2.38 2.50 2.63 1.71 1.80 1.89 1.43 1.50 1.58 2.38 2.50 2.63 1.71 1.80 1.89 1.71 1.80 1.89 0 — 70 –40 — Lattice Semiconductor Corporation www.latticesemi.com °C °C Units °C °C °C ...
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... VREF–0.180 SSTL2 (Class 1) SSTL18 (Full) 1.8V VREF–0.125 SSTL18 (Half) NOTES: SSTL2 and SSTL18 I/O standards require the VREF input pin, which is only available on the CB284 package and die-based products. Lattice Semiconductor Corporation www.latticesemi.com Table 49: PIO Pin Electrical Characteristics Conditions V = VCCIO ...
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... Nom VCCIO VCCIO VCCIO 2 2 VCCIO VCCIO VCCIO 2 2 Differential output voltage OCM GND VCCIO_x 2 =| OUT_B OUT_A V (V) OCM Max Min Nom VCCIO VCCIO 400 2 2 VCCIO VCCIO 200 2 2 Lattice Semiconductor Corporation www.latticesemi.com Max 2 2 Max VCCIO 2 VCCIO 2 ...
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... I/O Banks and SPI Bank Characteristic Curves Figure 52: Typical LVCMOS Output Low Characteristics (I/O Banks and SPI) Figure 53: Typical LVCMOS Output High Characteristics (I/O Banks and SPI) Figure 54: Input with Internal Pull-Up Resistor Enabled (I/O Banks and SPI) Lattice Semiconductor Corporation www.latticesemi.com VCCIO = 1.8V 10 VCCIO = 1 ...
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... The following examples provide some guidelines of device performance. The actual performance depends on the specific application and how it is physically implemented in the iCE65 FPGA using the Lattice iCEcube software. The following guidelines assume typical conditions (VCC = 1 1 specified, temperature = 25 ˚C). Apply derating factors using the iCEcube timing analyzer to adjust to other operating regimes ...
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... Asynchronous delay from adjacent PADO connect interconnect to PIO output pad including output interconnect delay. Lattice Semiconductor Corporation www.latticesemi.com The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The Programmable I/O (PIO) Pad-to-Pad Timing Circuit PAD PIO Programmable I/O (PIO) Sequential Timing Circuit ...
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... Device: iCE65 Power/Speed Grade Nominal VCC Description PIO PAD RDATA GBUF GBIN RCLK L01 L04, L08 –T –L –L –T 1.2 V 1.0 V 1.2 V 1.2 V Typ. Typ. Typ. Typ. 0.6 3.1 1.7 0 5.6 17.1 9.1 7.3 2.1 7.3 3.8 2.6 0.54 1.14 0.54 0.54 0.63 1.32 0.63 0.63 1.27 2.64 1.27 1.27 256 256 256 256 Lattice Semiconductor Corporation www.latticesemi.com Figure 59. Units MHz ...
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... From To t CREST_B CREST_B CRESET_B t CDONE PIO pins DONE_IO High active Lattice Semiconductor Corporation www.latticesemi.com Table 57: Internal Oscillator Frequency Frequency (MHz) Min. Max. 4.0 6.8 Default oscillator frequency. Slow enough to safely operate with any SPI serial PROM Supported by most SPI serial Flash PROMs ...
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... Max. Typical Typical 100 Typical « 1 « 1 « 1 iCE65L01: « 1 iCE65L04/08: 1.2 « 1 Lattice Semiconductor Corporation www.latticesemi.com Max. Units — µs — ns — ns — ns — ns 1,000 ns 25 MHz Units Max. µA µA mA Max Units µA µ ...
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... Notes Lattice Semiconductor Corporation www.latticesemi.com (2.42, 30-MAR-2011) 107 ...
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... Table 35, and Table 46. Updated I/O Table 7. Correct ball numbers for showing the differences between the ‘L04 and ‘L08 in the Package and Pinout Information (Table 14, Table 13). Added “Automatic Global Buffer Insertion, Lattice Semiconductor Corporation www.latticesemi.com 48. 2, Table 48, and Table 58. 21. Changed 48. Table 61, and section ...
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... Updated package roadmap (Table 2) and updated ordering codes (Figure 2). Updated Figure 7. Updated Figure 24. Added CS63 package footprint (Figure 36), pinout (Table 39) and Package. 1.0 31-MAY-2008 Initial public release. Lattice Semiconductor Corporation www.latticesemi.com Figure 2 and Table Differential Inputs and Electrical Characteristics and AC Timing Guidelines Table 34 ...
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... Ultra Low-Power mobileFPGA © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...