iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 25

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Device Configuration
Lattice Semiconductor Corporation
www.latticesemi.com
Configuration Mode Selection
As described in
configuration bitstream image, generated by the Lattice development system. For high-volume applications, the
bitstream image is usually permanently programmed in the on-chip NVCM, However, the bitstream image can also
be stored external in a standard, low-cost commodity SPI serial Flash PROM. The iCE65 component can
automatically load the image using the
can be downloaded from an external processor, microcontroller, or DSP processor using an SPI-like serial interface
or an IEEE 1149 JTAG interface.
The iCE65 configuration mode is selected according to the following priority described below and illustrated in
Figure
Peripheral
SPI Flash
NVCM



Mode
JTAG
SPI
20.

After exiting the Power-On Reset (POR) state or when CRESET_B returns High after being held Low for
250 ns or more, the iCE65 FPGA samples the logical value on its SPI_SS_B pin. Like other programmable I/O
pins, the SPI_SS_B pin has an internal pull-up resistor (see
If the
If the
external controller or from another iCE65 device in SPI Master Configuration Mode using an SPI-like
interface.
Check if the iCE65 is enabled to configure from the Nonvolatile Configuration Memory (NVCM). If the
iCE65 device has NVCM memory (‘F’ ordering code) but the NVCM is yet unprogrammed, then the
iCE65 device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the
iCE65 device will configure from NVCM.


SPI_SS_B
SPI_SS_B
If enabled to configure from NVCM, the iCE65 device configures itself using NVCM.
If not enabled to configure from NVCM, then the iCE65 FPGA configures using the
Configuration
Microprocessor
Table
Peripheral
Processor
Analogy
JTAG
ASIC
pin is sampled as a logic ‘1’ (High), then …
pin is sampled as a logic ‘0’ (Low), then the iCE65 device waits to be configured from an
20, iCE65 components are configured for a specific application by loading a binary
Interface.
Table 20:
Internal, lowest-cost, secure, one-time programmable Nonvolatile Configuration
Memory (NVCM)
External, low-cost, commodity, SPI serial Flash PROM
Configured by external device, such as a processor, microcontroller, or DSP using
practically any data source, such as system Flash, a disk image, or over a network
connection.
JTAG configuration requires sending a special command sequence on the SPI
interface to enable JTAG configuration. Configuration is controlled by and external
device.
SPI Master Configuration
iCE65 Device Configuration Modes
Configuration Data Source
Interface. Similarly, the iCE65 configuration data
Input Pull-Up Resistors on I/O Banks 0, 1, and
(2.42, 30-MAR-2011)
SPI Master
2).
25