iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 103

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Lattice Semiconductor Corporation
www.latticesemi.com
t
t
t
t
t
t
Symbol
Programmable Input/Output (PIO) Block
OCKO
GBCKIO
SUPDIN
HDPDIN
PADIN
PADO
Table 55
shown in
iCEcube development software reports timing adjustments for other I/O standards.
connect
From
OUTFF
clock
input
GBIN
input
input
GBIN
input
input
Inter-
PIO
PIO
provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
Figure 57
Table 55:
Synchronous Output Paths
Synchronous Input Paths
Pad to Pad
connect
output
output
OUTFF
GBIN
clock
input
input
input
Inter-
PIO
PIO
PIO
To
Figure 57:
Figure 58:
and
Figure 58.
Typical Programmable Input/Output (PIO) Timing (LVCMOS25)
Delay from clock input on OUTFF output flip-
flop to PIO output pad.
Global Buffer Input (GBIN) delay, though
Global Buffer (GBUF) clock network to clock
input on the PIO OUTFF output flip-flop.
Setup time on PIO input pin to INFF input flip-
flop before active clock edge on GBIN input,
including interconnect delay.
Hold time on PIO input to INFF input flip-flop
after active clock edge on the GBIN input,
including interconnect delay.
Asynchronous delay from PIO input pad to
adjacent interconnect.
Asynchronous delay from adjacent
interconnect to PIO output pad including
interconnect delay.
GBIN
Programmable I/O (PIO) Pad-to-Pad Timing Circuit
Programmable I/O (PIO) Sequential Timing Circuit
PAD
PAD
GBUF
The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The
Description
PIO
PIO
D
INFF
Power/Speed Grad
Q
Device: iCE65
Nominal VCC
D
OUTFF
Q
1.2 V
Typ.
L01
4.7
2.1
2.7
2.5
4.5
–T
0
PIO
PIO
1.0 V
Typ.
13.8
14.6
7.3
7.1
9.5
0
PAD
PAD
–L
L04, L08
1.2 V
Typ.
7.3
3.8
3.6
5.0
7.7
(2.42, 30-MAR-2011)
0
1.2 V
Typ.
5.6
2.6
2.8
3.2
6.2
–T
0
Units
103
ns
ns
ns
ns
ns
ns