iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 40

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
40
iCE65 Pin Descriptions
Table 36
the associated I/O bank. The table also indicates if the signal has an internal pull-up resistor enabled during
configuration. Finally, the table describes the function of the pin.
CDONE
CRESET_B
GBIN0/PIO0
GBIN1/PIO0
GBIN2/PIO1
GBIN3/PIO1
GBIN4/PIO2
GBIN5/PIO2
GBIN6/PIO3
GBIN7/PIO3
GND
PIOx_yy
PIO2/CBSEL0
PIO2/CBSEL1
PIO3_yy/
DPwwz
PIOS/SPI_SO
PIOS /SPI_SI
PIOS /
SPI_SS_B
PIOS/
SPI_SCK
TDI
Signal Name
lists the various iCE65 pins, alphabetically by name. The table indicates the directionality of the signal and
Direction
Input/IO
Input/IO
Input/IO
Input/IO
Input/IO
Input/IO
Input/IO
Output
Supply
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
Bank
0,1,2
I/O
SPI
SPI
SPI
SPI
All
2
2
0
1
2
3
3
2
2
3
1
Table 36: iCE65 Pin Description
Pull-up
during
Config
Yes
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
™
Configuration Done. Dedicated output. Includes a permanent
weak pull-up resistor to VCCIO_2.. If driving external devices
with CDONE output, connect a 10 kΩ pull-up resistor to
VCCIO_2.
Configuration Reset, active Low. Dedicated input. No internal
pull-up resistor. Either actively drive externally or connect a
10 kΩ pull-up resistor to VCCIO_2.
Global buffer input from I/O Bank 0. Optionally, a full-featured
PIO pin.
Global buffer input from I/O Bank 1. Optionally, a full-featured
PIO pin.
Global buffer input from I/O Bank 2. Optionally, a full-featured
PIO pin.
Global buffer input from I/O Bank 3. Optionally, a full-featured
PIO pin.
Global buffer input from I/O Bank 3. Optionally, a full-featured
PIO pin. Optionally, a differential clock input using the
associated differential input pin.
Ground. All must be connected.
Programmable I/O pin defined by the iCE65 configuration
bitstream. The ‘x’ number specifies the I/O bank number in
which the I/O pin resides. The “yy’ number specifies the I/O
number in that bank.
Optional ColdBoot configuration SELect input, if ColdBoot mode
is enabled. A full-featured PIO pin after configuration.
Optional ColdBoot configuration SELect input, if ColdBoot mode
is enabled. A full-featured PIO pin after configuration.
Programmable I/O pin that is also half of a differential I/O pair.
Only available in I/O Bank 3. The “yy” number specifies the I/O
number in that bank. The “ww” number indicates the
differential I/O pair. The ‘z’ indicates the polarity of the pin in
the differential pair. ‘A’=negative input. ‘B’=positive input.
SPI Serial Output. A full-featured PIO pin after configuration.
SPI Serial Input. A full-featured PIO pin after configuration.
SPI Slave Select. Active Low. Includes an internal weak pull-up
resistor to SPI_VCC during configuration. During configuration,
the logic level sampled on this pin determines the configuration
mode used by the iCE65 device, as shown in
input when sampled at the start of configuration. An input when
in SPI Peripheral configuration mode (SPI_SS_B = Low). An
output when in SPI Flash configuration mode. A full-featured
PIO pin after configuration.
SPI Slave Clock. An input when in SPI Peripheral configuration
mode (SPI_SS_B = Low). An output when in SPI Flash
configuration mode. A full-featured PIO pin after configuration.
JTAG Test Data Input. If using the JTAG interface, use a 10kΩ
pull-up resistor to VCCIO_1. Tie off to GND when unused.
Family
Lattice Semiconductor Corporation
Description
www.latticesemi.com
Figure
20. An