iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 13

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Lattice Semiconductor Corporation
www.latticesemi.com
Differential Outputs in Any Bank
Differential outputs are built using a pair of single-ended PIO pins as shown in
requires a three-resistor termination network to adjust output characteristic to match those for the specific
differential I/O standard. The output characteristics depend on the values of the parallel resistors (RP) and series
resistor (RS). Differential outputs must be located in the same I/O tile.
For electrical characteristics, see
The PIO pins that make up a differential output pair are indicated with a blue bounding box in the in the tables in
“Die Cross
Reference” starting on page 84.
Figure 8:
Differential Inputs in iCE65L04 and iC65L08 I/O Bank 3
“Differential
iC65 Differential Output Pair
1
Figure 9: Differential Output Pair
termination resistor
1
External 100Ω
50Ω
50Ω
VCCIO_x
Outputs” on page 100.
Impedance-matched
0
signals remains nearly constant.
signal traces
Noise pulse affects both traces
similarly. Difference between
0
Noise pulse affects both traces
similarly. Difference is signals
remains nearly constant.
R
R
S
S
iC65 Differential
VCCIO_3 = 1.8V or 2.5V
resistor network
External output
R
compensation
P
1
Input
1
DPxxB
DPxxA
50Ω
50Ω
0
Figure
0
Impedance-matched
signal traces
9. Each differential I/O pair
(2.42, 30-MAR-2011)
13