iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 18

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
18
Global Routing Resources
Global Buffers
Each iCE65 component has eight global buffer routing connections, illustrated in
drive buffers, connected to the eight low-skew, global lines. These lines are designed primarily for clock distribution
but are also useful for other high-fanout signals such as set/reset and enable signals. The global buffers originate
either from the Global Buffer Inputs (GBINx) or from programmable interconnect. The associated GBINx pin
represents the best pin to drive a global buffer from an external source. However, the application with an iCE65
FPGA can also drive a global buffer via any other PIO pin or from internal logic using the programmable
interconnect.
If not used in an application, individual global buffers are turned off to save power.
Table 11
All global buffers optionally connect to all clock inputs. Any four of the eight global buffers can drive logic inputs to
a PLB. Even-numbered global buffers optionally drive the Reset input to a PLB. Similarly, odd-numbered buffers
optionally drive the PLB clock-enable input.
Global Buffer
GBUF0
GBUF1
GBUF2
GBUF3
GBUF4
GBUF5
GBUF6
GBUF7
lists the connections between a specific global buffer and the inputs on a Programmable Logic Block (PLB).
Table 11:
Figure 14:
Global Buffer (GBUF) Connections to Programmable Logic Block (PLB)
High-drive, Low-skew, High-fanout Global Buffer Routing Resources
Yes, any 4 of 8
GBUF buffers
LUT Inputs
GBIN6
GBIN7
GBUF7
GBUF6
Global
Buffer
Global
Buffer
GBUF7 and its associated
PIO are best for direct
differential clock inputs
I/O Bank 0
I/O Bank 2
™
Family
Clock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Global
GBUF2
GBUF3
Global
Buffer
Buffer
Clock Enable
Lattice Semiconductor Corporation
GBIN2
GBIN3
Yes
Yes
Yes
Yes
No
No
No
No
Figure
14. There are eight high-
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Reset
Yes
Yes
Yes
Yes
No
No
No
No