iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 41

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Lattice Semiconductor Corporation
www.latticesemi.com
iCE65 Package Footprint Diagram Conventions
Figure 31
with an I/O Bank. PIO pins in I/O Bank 3 that support differential inputs are also numbered by differential input
pair.
TMS
TCK
TDO
TRST_B
VCC
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
SPI_VCC
VPP_FAST
VPP_2V5
VREF
N/A = Not Applicable
Signal Name
illustrates the naming conventions used in the following footprint diagrams. Each PIO pin is associated
Direction
Reference
Voltage
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Figure 31:
Ball row number
Bank
Ball number A1
I/O
SPI
All
All
All
1
1
1
1
0
1
2
3
3
Differential
Indicators
Input Pair
CB Package Footprint Diagram Conventions
Pull-up
during
Config
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
No
No
No
No
A
B
C
DP07A
DP07B
PIO0
PIO3/
PIO3/
1
JTAG Test Mode Select. If using the JTAG interface, use a 10kΩ
pull-up resistor to VCCIO_1. Tie off to GND when unused.
JTAG Test Clock. If using the JTAG interface, use a 10kΩ pull-
up resistor to VCCIO_1. Tie off to GND when unused.
JTAG Test Data Output.
JTAG Test Reset, active Low. Keep Low during normal
operation; High for JTAG operation.
Internal core voltage supply. All must be connected.
Voltage supply to I/O Bank 0. All such pins or balls on the
package must be connected. Can be disconnected or turned off
without affecting the
Voltage supply to I/O Bank 1. All such pins or balls on the
package must be connected. Required to guarantee a valid
input voltage on
Voltage supply to I/O Bank 2. All such pins or balls on the
package must be connected. Required input to the
Reset (POR)
Voltage supply to I/O Bank 3. All such pins or balls on the
package must be connected. Can be disconnected or turned off
without affecting the
SPI interface voltage supply input. Must have a valid voltage
even if configuring from NVCM. Required input to the
Reset (POR)
Direct programming voltage supply. If unused, leave floating or
unconnected during normal operation.
Programming supply voltage. When the iCE65 device is active,
VPP_2V5 must be in the valid range between 2.3 V to 3.47 V to
release the Power-On Reset circuit, even if the application is not
using the NVCM.
Input reference voltage in I/O Bank 3 for the SSTL I/O standard.
This pin only appears on the CB284 package and for die-based
products.
Single-ended PIO Numbering
Differential Input Pair Numbering
Ball column number
PIO0
Dot indicates unconnected pin
for iCE65L04 in CB284 package
DP07A
PIO0/
circuit.
circuit.
TRST_B
I/O bank number
Pair pin polarity
Pair number
Differential Pair
Power-On Reset (POR)
Power-On Reset (POR)
JTAG pin.
Description
(2.42, 30-MAR-2011)
circuit.
circuit.
Power-On
Power-On
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