iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 7

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

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www.latticesemi.com
Carry Logic
Each flip-flop has an additional control that defines its set or reset behavior. As defined in the configuration image,
the control defines whether the set or reset operation is synchronized to the active CLK clock edge or whether it is
completely asynchronous.
The LUT4 output or the flip-flop output then connects to the programmable interconnect.
Because of the shared control signals, the design software can pack flip-flops with common control inputs into a
single PLB block, as described by
For detailed flip-flop internal timing, see
The dedicated Carry Logic within each Logic Cell primarily accelerates and improves the efficiency of arithmetic
logic such as adders, accumulators, subtracters, incrementers, decrementers, counters, ALUs, and comparators. The
Carry Logic also supports wide combinational logic functions.
Equation 1 and
the associated Look-Up Table (LUT4). The LUT4’s I1 and I2 inputs directly feed the Carry Logic; inputs I0 and I3
do not. A signal cascades between Logic Cells within the Programmable Logic Block. The carry input from the
previous adjacent Logic Cell optionally provides an alternate input to the LUT4 function, supplanting the I3 input.
Low-Power Disable
To save power and prevent unnecessary signal switching, the Carry Logic function within a Logic Cell is disabled if
not used. The output of a Logic Cell’s Carry Logic is forced High.
PLB Carry Input and Carry Output Connections
As shown in
come from the carry output signal from PLB immediately below.
Similarly, the Carry Logic output from the Programmable Logic Block connects to the PLB immediately above,
which allows the Carry Logic to span across multiple PLBs in a column. As shown in
can be tapped mid-way through a chain or a PLB by feeding the value through a LUT4 function.
Adder Example
Figure 6
into an adder of arbitrary size. The LUT4 function within a Logic Cell is programmed to calculate the sum of the
two input values and the carry input, A[i] + B[i] + CARRY_IN[i-1] = SUM[i].


The SB_DFFR and SB_DFFS primitives are asynchronously controlled, solely by the SR input. If the SR
input is High, then an SB_DFFR primitive is asynchronously reset and an SB_DFFS primitive is
asynchronously set.
The SB_DFFSR and SB_DFFRSS primitives are synchronously controlled by both the SR input and the clock
input. If the SR input is High at a rising edge of the clock input, then an SB_DFFSR primitive is
synchronously reset and an SB_DFFSS primitive is synchronously set.
Group
shows an example design that uses the Carry Logic. The example is a 2-bit adder, which can be expanded
1
2
3
4
5
6
7
8
Figure
Figure 5
5, each Programmable Logic Block has a carry input signal that can be initialized High, Low, or
describe the Carry Logic structure within a Logic Cell. The Carry Logic shares inputs with
Table 4:
Active Clock Edge
Table
COUT = I1 ● I2 + CIN ●I1 + CIN ● I2








Flip-flop Packing/Sharing within a PLB
4. There are eight total packing options.
Table
54.
Selective (controlled by
None (always enabled)
PLB clock enable)
Clock Enable
Figure
Set or Reset Control
PLB set/reset control
PLB set/reset control
(Sync. or Async)
6, the Carry Logic chain
(2.42, 30-MAR-2011)
None
None
[Equation 1]
7