iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 102

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

iCE65 Ultra Low-Power mobileFPGA
AC Timing Guidelines
(2.42, 30-MAR-2012)
102
F
t
t
t
t
t
t
t
Symbol
CKO
GBCKLC
SULI
HDLI
LUT4IN
ILO
LUT4IN
Programmable Logic Block (PLB) Timing
TOGGLE
The following examples provide some guidelines of device performance. The actual performance depends on the
specific application and how it is physically implemented in the iCE65 FPGA using the Lattice iCEcube software.
The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply
derating factors using the iCEcube timing analyzer to adjust to other operating regimes.
Table 54
shown in
output
From
GBIN
input
clock
input
GBIN
input
input
GBIN
input
input
LUT4
input
LUT4
DFF
PIO
PIO
provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
Figure 55
Sequential Logic Paths
Combinational Logic Paths
output
output
output
GBIN
GBIN
LUT4
LUT4
input
clock
input
input
input
input
PIO
DFF
PIO
PIO
To
and
Table 54:
Figure
Flip-flop toggle frequency. DFF flip-flop output fed back to
LUT4 input with 4-input XOR, clocked on same clock edge.
Logic cell flip-flop (DFF) clock-to-output time, measured
from the DFF CLK input to PIO output, including
interconnect delay.
Global Buffer Input (GBIN) delay, though Global Buffer
(GBUF) clock network to clock input on the logic cell DFF
flip-flop.
Minimum setup time on PIO input, through LUT4, to DFF
flip-flop D-input before active clock edge on the GBIN
input, including interconnect delay.
Minimum hold time on PIO input, through LUT4, to DFF
flip-flop D-input after active clock edge on the GBIN input,
including interconnect delay.
Asynchronous delay from PIO input pad to adjacent PLB
interconnect.
Logic cell LUT4 combinational logic propagation delay,
regardless of logic complexity from input to output.
Asynchronous delay from adjacent PLB interconnect
to PIO output pad.
GBIN
PAD
PAD
Figure 56
56.
Figure 55 PLB Sequential Timing Circuit
Typical Programmable Logic Block (PLB) Timing
GBUF
PIO
PIO
Description
PLB Combinational Timing Circuit
LUT4
LUT4
™
Power/Speed Grade
Family
Logic Cell
Logic Cell
Device: iCE65
Logic Cell
Nominal VCC
D
DFF
Q
1.2 V
Typ.
L01
256
5.4
2.2
1.0
2.6
0.6
4.9
–T
PIO
PIO
0
Lattice Semiconductor Corporation
PAD
PAD
1.0 V
Typ.
16.5
16.0
224
7.3
4.0
9.8
1.9
0
–L
L04, L08
1.2 V
Typ.
256
8.7
3.8
2.1
5.2
1.0
8.4
0
www.latticesemi.com
1.2 V
Typ.
256
7.1
2.7
1.2
3.3
0.6
6.6
–T
0
Units
MHz
ns
ns
ns
ns
ns
ns
ns