iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 21

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

RAM
Lattice Semiconductor Corporation
www.latticesemi.com
Automatic Global Buffer Insertion, Manual Insertion
The iCEcube development software automatically assigns high-fanout signals to a global buffer. However, to
manual insert a global buffer input/global buffer (GBIN/GBUF) combination, use the SB_IO_GB primitive. To
insert just a global buffer (GBUF), use the SB_GB primitive.
Global Hi-Z Control
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE65 device. This GHIZ signal is
automatically asserted throughout the configuration process, forcing all user-I/O pins into their high-impedance
state. Similarly, the PIO pins can be forced into their high-impedance state via the JTAG controller.
Global Reset Control
The global reset control signal connects to all PLB and PIO flip-flops on the iCE65 device. The global reset signal is
automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state.
For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.
See
The PIO flip-flops are always reset during configuration, although the output flip-flop can be inverted before leaving
the iCE65 device, as shown in
Each iCE65 device includes multiple high-speed synchronous RAM blocks (RAM4K), each 4Kbit in size. As shown
in
deep by 16-bit wide, two-port register file, as illustrated in
from a RAM4K block, feed into the programmable interconnect resources.
Using programmable logic resources, a RAM4K block implements a variety of logic functions, each with
configurable input and output data width.
iCE65L01
iCE65L04
iCE65L08
Table 16
Device
Table 3



Random-access memory (RAM)
Single-port RAM with a common address, enable, and clock control lines
Two-port RAM with separate read and write control lines, address inputs, and enable
for more information.
a single iCE65 integrates between 16 to 96 such blocks. Each RAM4K block is generically a 256-word
RAM4K Blocks
16
20
32
Figure
WDATA[15:0]
WADDR[7:0]
MASK[15:0]
Write Port
Table 16: RAM4K Blocks per Device
Figure 17: RAM4K Memory Block
11.
WCLKE
WCLK
WE
Configuration
256 x 16
Default
RAM Block
(256x16)
RAM4K
Figure
RAM Bits per Block
RDATA[15:0]
17. The input and output connections, to and
RADDR[7:0]
(4,096)
Read Port
4K
RCLKE
RCLK
RE
(2.42, 30-MAR-2011)
Block RAM Bits
128K
64K
80K
21