iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 15

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

Lattice Semiconductor Corporation
www.latticesemi.com
Output and Output Enable Signal Path
For additional information on using the iCEgate feature, please refer to the following application note.
Input Pull-Up Resistors on I/O Banks 0, 1, and 2
The PIO pins in I/O Banks 0, 1, and 2 have an optional input pull-up resistor. Pull-up resistors are not provided in
iCE65L04 and iCE65L08 I/O Bank 3. During the iCE65 configuration process, the input pull-up resistor is
unconditionally enabled and pulls the input to within a diode drop of the associated I/O bank supply voltage
(VCCIO_#). This prevents any signals from floating on the circuit board during configuration.
After iCE65 configuration is complete, the input pull-up resistor is optional, defined by a configuration bit. The
pull-up resistor is also useful to tie off unused PIO pins. The Lattice iCEcube development software defines all
unused PIO pins in I/O Banks 0, 1 and 2 as inputs with the pull-up resistor turned on. The pull-up resistor value
depends on the VCCIO voltage applied to the bank, as shown in
No Input Pull-up Resistors on I/O Bank 3 of iCE65L04 and iCE65L08
The PIO pins in I/O Bank 3 do not have an internal pull-up resistor. To minimize power consumption, tie unused
PIO pins in Bank 3 to a known logic level or drive them as a disabled high-impedance output.
Input Hysteresis
Inputs typically have about 50 mV of hysteresis, as indicated in
As shown in
This output connects either directly to the associated package pin or is held in an optional output flip-flop. Because
all flip-flops are automatically reset after configuration, the output from the output flip-flop can be optionally
inverted so that an active-Low output signal is held in the disabled (High) state immediately after configuration.
Similarly, each Programmable I/O pin has an output enable or three-state control called OE. When OE = High, the
OUT output signal drives the associated pad, as described in
high-impedance (Hi-Z) state. The OE output enable control signal itself connects either directly to the output
buffer or is held in an optional register. The output buffer is optionally permanently enabled or permanently
disabled, either to unconditionally drive output signals, or to allow input-only signals.
See
Three-State
Drive Output Data
X = don’t care, 1* = High or unused, Hi-Z = high-impedance, three-stated, floating.
i
Input and Output Register Control per PIO Pair
AN002: Using iCEgate Blocking for Ultra-Low Power
!
For best possible performance, the global buffer inputs (GBIN[7:-0]) connect directly to the their associated
global buffers (GBUF[7:0]), bypassing the PIO logic and iCEgate circuitry as shown in
Consequently, the direct GBIN-to-GBUF connection cannot be blocked by the iCEgate circuitry. However,
it is possible to use iCEgate to block PIO-to-GBUF clock connections.
Table 10:
Figure
Note: JTAG inputs TCK, TDI and TMS do not have the input pull-up resistor and must be tied off to GND
when unused, else VCCIO_1 draws current.
7, a signal from programmable interconnect feeds the OUT signal on a Programmable I/O pad.
Operation
PIO Output Operations (non-registered operation, no inversions)
for information about the registered input path.
Data Output
Table
Table
Table
OUT
OUT
X
10. When OE = Low, the output driver is in the
49.
49.
Enable
OE
1*
0
(2.42, 30-MAR-2011)
PAD
OUT
Hi-Z
Figure
15
7.