iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 6

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
6
Look-Up Table (LUT4)
‘D’-style Flip-Flop (DFF)
The four-input Look-Up Table (LUT4) function implements any and all combinational logic functions, regardless of
complexity, of between zero and four inputs. Zero-input functions include “High” (1) and “Low” (0). The LUT4
function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the
as shown in
from the previous Logic Cell.
The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the
flip-flop output then connects to the programmable interconnect.
For detailed LUT4 internal timing, see
The ‘D’-style flip-flop (DFF) optionally stores state information for the application.
The flip-flop has a data input, ‘D’, and a data output, ‘Q’. Additionally, each flip-flop has up to three control signals
that are shared among all flip-flops in all Logic Cells within the PLB, as shown in
behavior of the flip-flop based on inputs and upon the specific DFF design primitive used or synthesized.
The CLK clock signal is not optional and is shared among all flip-flops in a Programmable Logic Block. By default,
flip-flops are clocked by the rising edge of the PLB clock input, although the clock polarity can be inverted for all the
flip-flops in the PLB.
The CLK input optionally connects to one of the following clock sources.
The EN clock-enable signal is common to all Logic Cells in a Programmable Logic Block. If the enable signal is not
used, then the flip-flop is always enabled. This condition is indicated as “1*” in
this is the default state if the control signal is not connected in the application.
Similarly, the SR set/reset signal is common to all Logic Cells in a Programmable Logic Block. If not used, then the
flip-flop is never set/reset, except when cleared immediately after configuration or by the Global Reset signal. This
condition is indicated as “0*” in
not connected in the application.
All
SB_DFFR
SB_DFFS
SB_DFFSR
SB_DFFSS
X = don’t care, ↑ = rising clock edge (default polarity), 1* = High or unused, 0* = Low or unused
Primitive


DFF
The output from any one of the eight
A connection from the general-purpose interconnect fabric
Figure
Cleared Immediately after
Configuration
Hold Present Value
(Disabled)
Hold Present Value (Static
Clock)
Load with Input Data
Asynchronous Reset
Asynchronous Set
Synchronous Reset
Synchronous Set
4. The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output
Operation
Table
Table 3: ‘D’-Style Flip-Flop Behavior
Table
3. The asterisk indicates that this is the default state if the control signal is
54.
Global
Asynchronous
Asynchronous
Synchronous
Synchronous
Flip-Flop
Mode
Reset
Reset
™
Set
Set
Buffers, or
X
Family
D
X
X
X
D
X
X
X
X
EN
1*
1*
1*
X
0
X
X
X
Inputs
Lattice Semiconductor Corporation
Table
SR
0*
X
X
X
1
1
1
1
Figure
3. The asterisk indicates that
1 or 0
CLK
X
X
↑
X
X
↑
↑
4.
Carry Logic
Table 3
www.latticesemi.com
Output
describes the
Q
Q
Q
D
0
0
1
0
1
function,