iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 28

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
28
Internal Oscillator
Internal Device Reset
Figure 21
numbers for the configuration control pins by package. When driven Low for at least 200 ns, the dedicated
Configuration Reset input, CRESET_B, resets the iCE65 device. When CRESET_B returns High, the iCE65 FPGA
restarts the configuration process from its power-on conditions
with no internal pull-up resistor. If driven by open-drain driver or un-driven, then connect the CRESET_B pin to a
10 kΩ pull-up resistor connected to the
The iCE65 device signals the end of the configuration process by actively turning off the internal pull-down
transistor on the Configuration Done output pin, CDONE. The pin has a permanent, weak internal pull-up resistor
to the
pull-up resistor connected to the VCCIO_2 supply.
The PIO pins activate according to their configured function after 49 configuration clock cycles. The internal
oscillator is the configuration clock source for the
* Note: only 14
Nonvolatile Configuration Memory (NVCM).
configuration clock source is the
During SPI Master or NVCM configuration mode, the controlling clock signal is generated from an internal
oscillator. The oscillator starts operating at the
settings within the configuration bitstream can specify a higher-frequency mode in order to maximize SPI
bandwidth and reduce overall configuration time. See
specified oscillator frequency range.
Using the
serial Flash PROM via the
The oscillator output, which also supplies the SPI SCK clock output during the SPI Flash configuration process, has
a 50% duty cycle.
Figure 22



Configuration
Control Pins
CRESET_B
VCCIO_2
CDONE
Power-On Reset (POR)
CRESET_B Pin
JTAG Interface
presents the various signals that internally reset the iCE65 internal logic.
shows the two iCE65 configuration control pins,
SPI Master Configuration
of the 16 RAM4K Memory Blocks may be pre-initialized in the iCE65L01.
rail. If the iCE65 device drives other devices, then optionally connect the CDONE pin to a 10 kΩ
Pulse
CRESET_B
Low for 200
ns to restart
configuration
Table 23:
SPI_SCK
CB81
H6
J6
Low resets iCE65
Figure 21: iCE65 Configuration Control Pins
Required if driven by
open-drain output
Optional Pull-up
Configuration Control Ball/Pin Numbers by Package
SPI_SCK
10 kΩ
clock output pin.
VCCIO_2
Interface, internal oscillator controls all the interface timing and clocks the SPI
Rising edge starts
configuration process.
VCCIO_2
clock input pin.
CRESET_B
QN84
A21
B16
Default
supply.
SPI Master Configuration Interface
When using the
™
SiliconBlue
I/O Bank 2
Family
iCE65
Table 57: Internal Oscillator Frequency
frequency. During the configuration process, however, bit
VQ100
44
43
CRESET_B
Unconfigured
CDONE
(Cold
Recommended if
driving another device
VCCIO_2
Optional Pull-up
SPI Peripheral Configuration
10 kΩ
Boot). The CRESET_B pin is a pure input
Configured
and CDONE.
CB132
M10
L10
Lattice Semiconductor Corporation
PIOs activate 49
configuration clock
cycles after CDONE
goes High
and when configuring from
Table 23
CB196
M10
L10
www.latticesemi.com
on page
lists the ball/pin
Interface, the
105
CB284
R14
T14
for the