iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 108

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

iCE65 Ultra Low-Power mobileFPGA
Revision History
(2.42, 30-MAR-2012)
108
Version
2.2.3
2.2.2
2.2.1
2.1.1
2.0.1
2.42
2.41
1.5.1
1.4.4
1.4.3
1.4.2
1.4.1
2.4
2.3
2.2
2.1
2.0
1.5
1.4
30-MAR-2012
1-AUG-2011
13-MAY-2011
18-OCT-2010
12-OCT-2010
8-OCT-2010
5-OCT-2010
6-AUG-2010
26-MAY-2010
14-SEPT-2009
15-MAR-2010
12-NOV-2009
25-MAR-2009
20-JUN-2009
27-FEB-2009
24-FEB-2009
13-JUL-2009
9-MAR-2009
9-FEB-2009
Date
Changed company name. Updated
Added VQ100 marking for NVCM programming.
Added L01 CB121 package
inputs TCK, TDI and TMS do not have the input pull-up resistor and must be tied off to
GND when unused,
package drawing,
increased thermal resistance. Added Marking Format and Thermal resistance to CB81
Packag Mechanical Drawing
Mechanical Drawing
Added L01 CB81 and L08 CB132 packages.
Changed
Configuration Process
and 1200 µs for iCE65L08.
Added iCE65L04 marking specification to
Changed FSPI_SCK from 0.125 MHz to 1 MHz in
and in
Programmable Interconnect section removed.
Switched labels on
Added JTAG unused input tie off guideline. Added marking specification and thermal
characteristics to package drawings. Added production datasheet for iCE65L01 with
timing update, including QN84, VQ100 and CB132. Added NVCM shut-off on SPI
configuration. Added non-standard VCCIO operating conditions.
voltage supply specification for LVCMOS33 to 3.14V in
Recommended Operation Conditions, Table 47, replaced junction with ambient.
Finalized production data sheet for iCE65L04 and iCE65L08. Improved SubLVDS input specification
V
datasheet. Added
Board Layout
Updated the text in
Updated timing information and added –T high-speed device option (affected
Table 54, Table
(affected
about the
Warm Boot operation can only jump to another configuration image that has Warm Boot disabled.
Updated configuration image size and configuration time for the iCE65L02 in
Reduced the minimum voltage supply specification for LVCMOS33 to 2.7V in
information about which power rails can be disconnected without effecting the Power-On Reset
(POR) circuit and clarified description of VPP_2V5 pin in
curves
timing per Figures 54-58 and Tables 55-57.
Clarified the voltage requirements for the VPP_2V5 pin in
Removed volatile-only (-V) product offering from
for ball T22 on CB284 package
Updated
Bank 3 information in
Based on characterization data, reduced 32KHz operating current by 40% in Table 1,
Figure
GBIN4/GBIN5 for CS110
iCE65L08 in CB196
CB196 package. Unified the package footprint nomenclature in the
Added note to
Added tables showing the ball/pin number for various control functions, by package
26, Table 30, and
GBIN6 and GBIN7. This change affected all pinout tables and footprint diagrams. Updated and corrected
“Differential Global Buffer
buffers and various resources
Manual
Added footprint and pinout information for the VQ100 Very-thin Quad Flat Package. Added footprint for
ICM
in
1. Corrected that SSTL18 standards require VREF pin in
Insertion.” Added
Table
(Figure
Table
Table
Figure
SPI Peripheral Configuration Interface
Figure 29: Application Processor Waveforms for SPI Peripheral Mode
Global Buffer Inputs
52. CS63 and CC72 packages removed and placed in iCE DiCE KGD, Known Good Die
Information”.
60.
52,
14,
55,
Table
7,
(Figure
Figure
“IBIS Models for I/O Banks 0, 1, 2 and the SPI
Table
Table
“SPI PROM
Table
Figure 35,
Figure 53
33). Corrected the GBIN/GBUF designations. GBIN4 and GBIN5 were swapped as were
Table
Table 7
Figure 37
Input.” Tested and corrected the clock-enable and reset connections between global
“Die Cross
46) and added
and
package.
23,
5,
53, and
56, and
(Table
Table
™
32. Input pin leakage current
Table
Table 60
and
Figure
(Figure
Figure 33.
LVCMOS Output High, VCCIO = 1.8V with VCCIO = 2.5V.
Requirements” section.
that the differential clock direct input is not available on the CB132 package.
Family
added note “underside metal is at ground potential”,
11,
Reference” section. Improved industrial temperature range by lowering
Figure
7,
Table
Table
26, Table 30,
Table
Table
Table 43
39. Added note “else VCCIO_1 draws current” to JTAG
Table 1
48).
from 300 µs CRESET_B to 800 µs for iCE65L01/04
61). Added support for 3.3V LVCMOS I/Os in I/O Bank 3
48.
54). Minor changes to
12, and
8,
Description
Added coplanarity specification to VQ100 Package
Table
Figure 47
showing the differences between the ‘L04 and ‘L08 in the
and timing in
Figure
Table
Table
47,
Table
13). Added
SPI Peripheral Configuration Interface
33,
Table
Table
2. Corrected NC on ball V22, removed it
CB196 Package Mechanical Drawing.
Lattice Semiconductor Corporation
Table 36
inor label change in
Table
Package and Pinout Information
48.
48, and
Table 49
36. Added I/O characterization
Table
Table
Figure 20
35, and
“Automatic Global Buffer Insertion,
Bank”. Added
and notes under
60. Added a warning that a
7. Correct ball numbers for
Table
Increased the minimum
split by bank. QN84
Table
and
(Table
51). Added a section
Table
Table 27
Figure
Figure
www.latticesemi.com
Figure
46. Updated I/O
“Printed Circuit
14,
48. Added
Table
Table
2,
48.
Table
21. Changed
and
Table
section.
23,
48.
Table
61, and
Table
48,
58.