iCE65L08F-LCB196C Lattice, iCE65L08F-LCB196C Datasheet - Page 55

• Manufacturer Part Number: iCE65L08F-LCB196C
• Description: FPGA - Field Programmable Gate Array iCE65 7680 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L08F-LCB196C

• Rohs: yes
• Number Of Gates: 7680
• Number Of Logic Blocks: 32
• Number Of I/os: 150
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-196
• Distributed Ram: 128 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 54 uA
• Factory Pack Quantity: 248

CB121 Chip-Scale Ball-Grid Array
Lattice Semiconductor Corporation
www.latticesemi.com
The CB121 package is a chip-scale, fully-populated, ball-grid array with 0.5 mm ball pitch.
Footprint Diagram
Figure 39
Also see
The signal pins are also grouped into the four I/O Banks and the SPI interface.
Pinout Table
Table 40
arranged by I/O bank, then by ball function.
Table 40
provides a detailed pinout table for the iCE65L01 in the CB121 chip-scale BGA package. Pins are generally
Ball Function
shows the iCE65L01 chip-scale BGA footprint for the 6 x 6 mm CB121 package.
GBIN0/PIO0
GBIN1/PIO0
PIO0
PIO0
PIO0
A
B
C
D
E
F
G
H
J
K
L
for a complete, detailed pinout for the 121-ball chip-scale BGA packages.
VCCIO_3
GND
VCC
PIO3
PIO3
PIO3
PIO3
PIO3
PIO3
NC
NC
1
1
Figure 39:
VCCIO_3
PIO0 PIO0
GND
GND
PIO2 PIO2
PIO3
PIO3
PIO3
PIO3
PIO3
PIO3
Table 40:
2
2

GBIN7/
PIO0
PIO3
PIO3
PIO2
PIO3
PIO3
PIO3
PIO3
PIO3
3
3
iCE65L01 CB121 Chip-Scale BGA Footprint (Top View)
I/O Bank 2
I/O Bank 0
GBIN6/
PIO0
PIO2
PIO2
PIO0
PIO2
PIO2
Ball Number
iCE65L01 CB121 Chip-scale BGA Pinout Table
PIO3
PIO3
PIO3
PIO3
PIO3
4
4
D6
C6
A2
A3
A4
VCCIO_2
GND
PIO0
PIO0
PIO0
PIO0
PIO0 PIO0
GND
PIO2
PIO2
PIO2
5
5
CBSEL1
GBIN1/
GBIN0/
CBSEL0
PIO2/
PIO2/
GND
GND
PIO0
PIO0
PIO0
VCC
VCC
NC
6
6
CRESET_B
VCCIO_0
CDONE
PIO0
PIO0
PIO0
PIO1
PIO0
PIO1
NC PIO0
NC
7
7
GBIN3/
GBIN4/
PIOS/
SPI_SO
PIOS/
PIO0
PIO0
PIO1
PIO1
PIO1
PIO1
PIO1 PIO1
SPI_SI
PIO2
8
8
SPI Bank
Pin Type
SPI_SS_B
SPI_SCK
GBIN2/
GBIN5/
PIOS/
PIOS/
PIO0
PIO0
PIO1
PIO1
PIO1
PIO1
PIO2
VPP_
FAST
GBIN
GBIN
PIO
PIO
PIO
9
9
VCCIO_1
PIO1
PIO1 PIO1
PIO1
PIO1
GND
GND
VPP_
PIO1
PIO2
SPI_
VCC
10 11
10 11
2V5
PIO1
PIO2
PIO2
PIO2
PIO1
PIO1
PIO1
GND
PIO2
VCC
A
B
C
D
E
F
G
H
J
K
L
(2.42, 30-MAR-2011)
Bank
0
0
0
0
0
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