ISL6334ACRZ Intersil, ISL6334ACRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6334ACRZ
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6334ACRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
current of all active channels, I
load-line regulation resistor R
across R
creating an output voltage droop with a steady-state value
defined as shown in Equation 8:
The regulated output voltage is reduced by the droop voltage
V
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed, as shown in Equation 9:
where V
programmed offset voltage, I
of the converter, R
the ISEN+ pin, and R
active channel number, and R
depending on the sensing method.
Therefore, the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
Output-Voltage Offset Programming
The ISL6334, ISL6334A allows the designer to accurately
adjust the offset voltage. When a resistor, R
connected between OFS to VCC, the voltage across it is
regulated to 1.6V. This causes a proportional current (I
to flow into OFS. If R
across it is regulated to 0.4V, and I
resistor between DAC and REF, R
the product (I
voltage. These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to calculate R
For Positive Offset (connect R
For Negative Offset (connect R
R
V
V
R
R
DROOP
OFS
DROOP
OUT
LL
OFS
=
=
=
=
------------
R
REF
0.4
----------------------------- -
. The output voltage as a function of load current is
N
FB
V
1.6
----------------------------- -
V
FB
V
=
REF
OFFSET
OFFSET
×
I
is proportional to the output current, effectively
×
----------------- -
R
AVG
is the reference voltage, V
OFS
R
R
ISEN
R
–
REF
REF
X
V
R
OFS
x R
ISEN
FB
OFS
FB
OFS
–
⎛
⎜
⎝
is the sense resistor connected to
I
---------------- -
is the feedback resistor, N is the
LOAD
is connected to ground, the voltage
) is equal to the desired offset
N
LOAD
19
FB
X
OFS
AVG
OFS
----------------- - R
R
is the DCR, or R
. The resulting voltage drop
ISEN
R
REF
, flows from FB through a
X
OFS
is the total output current
to VCC):
to GND):
, is selected so that
OFS
OFS
FB
flows out of OFS. A
⎞
⎟
⎠
:
OFS
is the
, is
SENSE
(EQ. 11)
ISL6334, ISL6334A
(EQ. 12)
(EQ. 10)
(EQ. 8)
(EQ. 9)
OFS
)
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs during regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner. Supervising
the safe output voltage transition within the DAC range of the
processor without discontinuity or disruption is a necessary
function of the core-voltage regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R
used. The selection of R
voltage as detailed in “Output-Voltage Offset Programming”
on page 19. The selection of C
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t
of R
During dynamic VID transition and VID steps up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50µs after
the transition.
C
REF
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
REF
R
REF
and C
1.6V
VID
=
VCC
+
REF
-
REF
, the relationship between the time constant
t
VID
network and t
0.4V
and C
E/A
GND
+
-
REF
REF
FB
is based on the desired offset
, as shown in Figure 7, can be
REF
VID
ISL6334, ISL6334A
DYNAMIC
is based on the time
VID D/A
is given by Equation 13.
May 28, 2009
DAC
OFS
GND
VCC
OR
(EQ. 13)
FN6482.1
REF
R
R
C
REF
REF
OFS