ISL6334ACRZ Intersil, ISL6334ACRZ Datasheet - Page 21

• Manufacturer Part Number: ISL6334ACRZ
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6334ACRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Current Sense Output
The current flowing out of the IMON pin is equal to the
sensed average current inside ISL6334, ISL6334A. In typical
applications, a resistor is placed from the IMON pin to GND
to generate a voltage, which is proportional to the load
current and the resistor value, as shown in Equation 17:
where V
resistor between the IMON pin and GND, I
output current of the converter, R
connected to the ISEN+ pin, N is the active channel number,
and R
either the DCR of the inductor or R
sensing method.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.11V
under the maximum load current. If the IMON pin voltage is
higher than 1.11V, overcurrent shutdown will be triggered, as
described in “Overcurrent Protection” on page 22.
A small capacitor can be placed between the IMON pin and
GND to reduce the noise impact. If this pin is not used, tie it
to GND.
Fault Monitoring and Protection
The ISL6334, ISL6334A actively monitors output voltage and
current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power-good indicator is provided for linking
to external system monitors. The schematic in Figure 10
outlines the interaction between the fault monitors and the
VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output which
indicates that the soft-start period has completed and the
output voltage is within the regulated range. VR_RDY is
pulled low during shutdown and releases high after a
V
IOUT
X
=
is the DC resistance of the current sense element,
IMON
------------------ -
R
IOUT
FIGURE 9. SOFT-START WAVEFORMS
N
is the voltage at the IMON pin, R
VOUT, 500mV/DIV
----------------- - I
R
ISEN
R
t
D1
X
EN_VTT
VR_RDY
LOAD
t
D2
500µs/DIV
21
t
ISEN
D3
SENSE
t
D4
is the sense resistor
t
depending on the
LOAD
D5
IMON
is the total
ISL6334, ISL6334A
(EQ. 17)
is the
successful soft-start and a fixed delay t
pulled low when an undervoltage or overvoltage condition is
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6334,
ISL6334A overvoltage protection (OVP) circuit will be active
after its POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during the
soft-start intervals t
1.273V. Once the controller detects valid VID input, the OVP
trip point will be changed to DAC plus 175mV.
Two actions are taken by ISL6334, ISL6334A to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs are
commanded low instantly (less than 20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level to avoid damaging the load. When
the VDIFF voltage falls below the DAC plus 75mV, PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both upper
and lower MOSFETs. If the overvoltage condition reoccurs,
ISL6334, ISL6334A will again command the lower MOSFETs to
turn on. ISL6334, ISL6334A will continue to protect the load in
this fashion as long as the overvoltage condition occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until ISL6334, ISL6334A is reset. Cycling
the voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
VID codes will not reset the controller..
VDIFF
FIGURE 10. VR_RDY AND PROTECTION CIRCUITRY
DAC
50%
VID + 0.175V
UV
D1
+
-
AND CONTROL LOGIC
OV
, t
SOFT-START, FAULT
D2
and t
D3
, the OVP threshold is
D5
. VR_RDY will be
OC
+
-
OC
1.11V
+
-
May 28, 2009
VR_RDY
IMON
FN6482.1
105µA
I
AVG