DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 124

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4
See
9.4.1 Receive Register Definitions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive CRC-16 Display (RCRCD).
Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that
this bit is a acknowledged reset. The host should set this bit and the DS26528 will clear it once the reset operation
is complete. The DS26528 will complete the HDLC reset within two frames.
Note: This bit will clear automatically if RMMR.INT_DONE has been set.
Bit 5: Receive HDLC Mapping Select (RHMS).
Bit 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to the
HDLC controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s selects
channel 32 (E1). A change to the receive HDLC channel select is acknowledged only after a receive HDLC reset
(RHR).
Table 9-3
Framer Register Definitions
0 = Do not write received CRC-16 code to FIFO (default)
1 = Write received CRC-16 code to FIFO after last octet of packet
0 = Normal operation
1 = Reset receive HDLC controller and flush the receive FIFO
0 = Receive HDLC assigned to channels
1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode)
RCRCD
for the complete framer register list.
7
0
RHC
Receive HDLC Control Register
010h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RHR
6
0
RHMS
5
0
RHCS4
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4
0
RHCS3
3
0
DS26528 Octal T1/E1/J1 Transceiver
RHCS2
2
0
RHCS1
1
0
RHCS0
0
0