DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 214

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit DS0 Channel Bits (B[1:8]). Transmit channel data that has been selected by the Transmit
DS0 Channel Monitor Select register (TDS0SEL). B8 is the LSB of the DS0 channel (last bit to be transmitted).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Blank Channel Select for Channels 1 to 32 (CH[1:32]).
Note that when two or more sequential channels are chosen to be ignored, the receive slip zone select bit should
be set to zero. If the ignore channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), the RSZS bit can be set to
one, which may provide a lower occurrence of slips in certain applications.
0 = transmit TSER data from this channel
1 = ignore TSER data from this channel
(MSB) 7
CH16
CH24
CH32
CH8
B1
0
7
0
CH15
CH23
CH31
CH7
TDS0M
Transmit DS0 Monitor Register
1BBh + (200h x n): where n = 0 to 7, for Ports 1 to 8
TBCS1, TBCS2, TBCS3, TBCS4
Transmit Blank Channel Select Registers 1 to 4
1C0h, 1C1h, 1C2h, 1C3h + (200h x n): where n = 0 to 7, for Ports 1 to 8
6
0
B2
6
0
CH14
CH22
CH30
CH6
5
0
B3
5
0
CH13
CH21
CH29
CH5
4
0
214 of 276
B4
4
0
CH12
CH20
CH28
CH4
3
0
B5
3
0
CH11
CH19
CH27
CH3
2
0
DS26528 Octal T1/E1/J1 Transceiver
B6
2
0
CH10
CH18
CH26
CH2
1
0
0 (LSB)
CH17
CH25
CH1
CH9
B7
1
0
0
TBCS1
TBCS2
TBCS3
TBCS4
(E1 Mode
Only)
B8
0
0