DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 68

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.10
8.10.1 Receive HDLC Controller
The DS26528 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). The HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as
specific Sa bits (E1 mode).
The HDLC controller performs all the necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
Table 8-33
Table 8-33. Registers Related to the HDLC
Receive HDLC Control Register (RHC)
Receive HDLC Bit Suppress Register
(RHBSE)
Receive HDLC FIFO Control Register
(RHFC)
Receive HDLC Packet Bytes Available
Register (RHPBA)
Receive HDLC FIFO Register (RHF)
Receive Real-Time Status Register 5
(RRTS5)
Receive Latched Status Register 5 (RLS5)
Receive Interrupt Mask Register 5 (RIM5)
Transmit HDLC Control Register 1(THC1)
Transmit HDLC Bit Suppress Register
(THBSE)
Transmit HDLC Control Register 2 (THC2)
Transmit HDLC FIFO Control Register
(THFC)
Transmit Real-Time Status Register 2
(TRTS2)
Transmit HDLC Latched Status Register 2
(TLS2)
Transmit Interrupt Mask Register 2 (HDLC)
Register (TIM2)
Transmit HDLC FIFO Buffer Available
Register (TFBA)
Transmit HDLC FIFO Register (THF)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 8 for Framers 2 to 8.
HDLC Controllers
shows the registers related to the HDLC.
REGISTER
ADDRESSES
FRAMER
68 of 276
0B5h
0B6h
0B4h
0A4h
1B1h
1A1h
1B3h
1B4h
010h
011h
087h
094h
110h
111h
113h
187h
191h
Mapping of the HDLC to DS0 or FDL.
Receive HDLC bit suppression register.
Determines the length of the receive HDLC
FIFO.
Tells the user how many bytes are available in
the teceive HDLC FIFO.
The actual FIFO data.
Indicates the FIFO status.
Latched status.
Interrupt mask for interrupt generation for the
latched status.
Miscellaneous transmit HDLC control.
Transmit HDLC bit suppress for bits not to be
used.
HDLC to DS0 channel selection and other
control.
Used to control the transmit HDLC FIFO.
Indicates the real-time status of the transmit
HDLC FIFO.
Indicates the FIFO status.
Interrupt mask for the latched status.
Indicates the number of bytes that can be
written into the transmit FIFO.
Transmit HDLC FIFO.
DS26528 Octal T1/E1/J1 Transceiver
FUNCTION