DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 21

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RSYSCLK
TCHBLK/
TCHBLK/
TCHBLK/
TCHBLK/
TCHBLK/
TCHBLK/
TCHBLK/
TCHBLK/
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
NAME
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
M11
M12
P11
D10
E11
B12
K13
E13
R10
P12
C11
D13
PIN
F11
J13
F13
L12
M4
A5
C7
P7
P9
E5
D6
N4
N6
G4
A4
B6
N5
L7
F4
L4
T6
TYPE
I/O
O
O
O
I
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low during any
of the channels. It is synchronous with TCLK when the transmit-side elastic store is
disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is
enabled. It is useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as Fractional T1, Fractional E1,
384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels
in drop-and-insert applications, for external per-channel loopback, and for per-
channel conditioning.
TCHCLK. TCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, TCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, TCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-to-
serial conversion of channel data. In either mode, TCHCLKn is synchronous with
TCLKn when the receive-side elastic store is disabled or it is synchronous with
TSYSCLKn when the receive-side elastic store is enabled. The mode of TCHCLK
is determined by the TGCLKEN bit in the TESCR register.
Received Serial Data. Received NRZ serial data. Updated on rising edges of
RCLK when the receive-side elastic store is disabled. Updated on the rising edges
of RSYSCLK when the receive-side elastic store is enabled.
When IBO mode is used, the RSER pins can output data for multiple framers. The
RSER data is synchronous to RSYSCLK. This is described in Section 8.8.2.
Receive Clock. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock
data through the receive-side framer. This clock is recovered from the signal at
RTIP and RRING. RSER data is output on the rising edge of RCLK. RCLK is used
to output RSER when the elastic store is not enabled or IBO is not used. When the
elastic store is enabled or IBO is used, the RSER is clocked by RSYSCLK.
Receive System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic store
function is enabled. Should be tied low in applications that do not use the receive-
side elastic store. Multiple of 2.048MHz is expected when the IBO mode is used.
Note that RSYSCLK is used for all eight transceivers.
Receive Synchronization. If the receive-side elastic store is enabled, then this
signal is used to input a frame or multiframe boundary pulse. If set to output frame
boundaries, then RSYNC can be programmed to output double-wide pulses on
signaling frames in T1 mode. In E1 mode, RSYNC out can be used to indicate
CAS and CRC-4 multiframe. The DS26528 can accept H.100-compatible
synchronization signal. The default direction of this pin at power-up is input, as
determined by the RSIO control bit in the RIOCR.2 register.
RECEIVE FRAMER
21 of 276
FUNCTION
DS26528 Octal T1/E1/J1 Transceiver